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datasheet r01ds0255ej0100 rev.1.00 page 1 of 106 feb 25, 2015 RX634 group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 54 mhz capable of 90 dmips in operation at 54 mhz ? two types of multiply-and-accumulation unit (between memories and between registers) ? 32-bit multiplier (fastest in struction execution takes one cpu clock cycle) ? divider (fastest instruction execution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions, ultra-compact code ? supports the memory protection unit (mpu) ? on-chip debugging circuit low power design and architecture ? operation from a single 2.7 to 3.6 v or 4.0 to 5.5 v supply ? four low power consumption modes on-chip main flash me mory, no wait states ? 54-mhz operation, 18.5-ns read cycle ? 1 to 2 mbytes supported ? user code is programmable by on-board on-chip data flash memory ? 32 kbytes capacities (number of times of reprogramming: 100,000) ? programming/erasing as bac kground operations (bgos) on-chip sram, no wait states ? 128-kbyte size capacities ? for instructions and operands dma ? dmac: incorporates four channels ? dtc elc ? module operation can be initiated by event signals without going through interrupts. ? modules can operate while the cpu is sleeping. reset and supply management ? power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? external crystal oscillator or internal pll for operation at 8 to 20 mhz ? internal 125-khz loco ? dedicated 125-khz loco for the iwdt ? clock frequency accuracy measurement circuit (cac) independent watchdog timer ? 125-khz on-chip oscillator produ ces a dedicated clock signal to drive iwdt operation. useful functions for iec60730 compliance ? oscillation-stoppage detectio n, frequency measurement, crc, iwdt, self-diagnostic f unction for the a/d converter, etc. various communications interfaces ? sci with many useful functions (up to 13 channels) asynchronous mode, clock s ynchronous mode, smart card interface, simplified spi, simplified i 2 c, and extended serial mode ? i 2 c bus interface: transfer at up to 400 kbps (three channels) ? rspi for high-speed transfer (two channels) cec transmission/reception function ? cec signals can be transmitted/ received conforming to cec standard 1.4 remote control signal reception ? two units integrated ? four pattern waveform matching supported external address space ? buses for high-speed data transfer (max. operating frequency of 27 mhz) ? 4 cs areas (4 16 mbytes) ? multiplexed bus or separate bus are selectable per area. ? 8-, or 16-bit bus space is selectable per area up to 20 extend ed-function timers ? 16-bit mtu: input capture, output compare, complementary pwm output, phase counting mode (six channels) ? 16-bit tpu: input capture, out put capture, phase counting mode (six channels) ? 8-bit tmr (four channels) ? 16-bit compare-match timers (four channels) 12-bit a/d converter ? capable of conversion within 1 s ? sample-and-hold circuits (for three channels) ? three-channel synchronized sampling available ? self-diagnostic function a nd analog input disconnection detection assistance function 10-bit d/a converter: 2 channels register write protection can protect values in important registers against overwriting up to 114 pins for general i/o ports ? open drain, input pull-up mpc ? multiple locations are selectab le for i/o pins of peripheral functions operating temperature range ?? 40 to +85 ? c plqp0144ka-a 20 20 mm, 0.5-mm pitch 54 mhz 32-bit rx mc u with fpu, 90 dmips, up to 2-mb yte flash memory, 12-bit adc, 10-bit dac, elc, mpc, cec transmission/reception, remote control signal reception r01ds0255ej0100 rev.1.00 feb 25, 2015
r01ds0255ej0100 rev.1.00 page 2 of 106 feb 25, 2015 RX634 group 1. overview 1.overview 1.1 outline of specifications table 1.1 lists the specifications in outline. table 1.1 outline of specifications (1 / 4) classification module/function description cpu cpu ? maximum operating frequency: 54 mhz ? 32-bit rx cpu ? minimum instruction exec ution time: one instruction per st ate (cycle of the system clock) ? address space: 4-gbyte linear ? register general purpose: sixteen 32-bit registers control: nine 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 ? floating-point instructions: 8 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 ? 32 ? 64 bits ? memory-protection unit (mpu) fpu ? single precision (32-bit) floating point ? data types and floating-point exceptions in conformance with the ieee754 standard memory rom ? capacity: 1 m/1.5 m/2 mbytes ? 54 mhz, no-wait memory access ? on-board programming: 3 types off-board programming ram ? capacity: 128 kbytes ? 54 mhz, no-wait memory access e2 dataflash ? capacity: 32 kbytes ? number of times for programming/erasing: 100,000 mcu operating mode single-chip mode, on-chip rom enabled expansion mode, and on-chip rom disabled expansion mode (software switching) clock clock generation circuit ? main clock oscillator, low-speed on-chip oscillator, pll frequency synthesizer, and iwdt-dedicated on-chip oscillator ? oscillation stop detection ? measuring circuit for accuracy of clo ck frequency (clock-accuracy check: cac) ? independent settings for the system clock (iclk), peripheral module clock (pclkb), external bus clock (bclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 54 mhz (at max.) peripheral modules run in synchronization with the peripheral module clock (pclkb): 32 mhz (at max.) devices connected to the external bus run in synch ronization with the external bus clock (bclk): 27 mhz (at max.) the flash peripheral circuit runs in synchronizati on with the flashif clock (fclk): 32 mhz (at max.) reset res# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog timer reset, deep software standby reset, and software reset voltage detection voltage detection circuit ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. the detection voltage level of voltage detection circuit 0 is fixed voltage detection circuit 1 is capable of selecting the detection voltage from 3 levels voltage detection circuit 2 is capable of selecting the detection voltage from 3 levels low power consumption low power consumption facilities ? module stop function ? four low power consumption modes sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode function for lower operating power consumption ? operating power control modes high-speed operating mode, low-speed operating mode 1, low-speed operating mode 2 interrupt interrupt controller (icub) ? interrupt vectors: 178 ? ext ernal interrupts: 14 (nmi, irq0 to irq12 pins) ? non-m a skable interrupts: 6 (the nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, wdt interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority
r01ds0255ej0100 rev.1.00 page 3 of 106 feb 25, 2015 RX634 group 1. overview external bus extension ? the external address space can be divided into four areas (cs0 to cs3), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs3) a chip-select signal (cs0# to cs3#) can be output for each area. each area is specifiable as an 8-bit or 16-bit bus space the data arrangement in each area is selectable as little or big endian (only for data). bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmaca) ? 4 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external in terrupts, and interrupt requests from peripheral functions data transfer controller (dtca) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 144-pin ? i/o: 114 ? input: 9 (p40 to p47, p35) ? pull-up resistors: 111 ? open-drain outputs: 114 ? 5-v tolerance: not supported event link controller (elc) ? event signals of 56 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for ports b and e multi-function pin controller (mpc) ? capable of selecting input/output function from multiple pins timers 16-bit timer pulse unit (tpua) ? (16 bits 6 channels) 1 unit ? maximum of 16 pulse-input/output possible ? select from among seven or eight coun ter-input clock signals for each channel ? supports the input capture/output compare function ? output of pwm waveforms in up to 15 phases in pwm mode ? support for buffered operation, phase-counting mode (two-phase encoder input) and cascade- connected operation (32 bits 2 channels) depending on the channel. ? capable of generating conversion start triggers for the a/d converters ? signals from the input capture pins are input via a digital filter multi-function timer pulse unit 2 (mtu2a) ? (16 bits ? 6 channels) ? 1 unit ? up to 16 pulse-input/output lines and three pulse-input lines are available with six 16-bit timer channels ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, mt clka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? generation of triggers for a/d converter conversion port output enable 2 (p oe2a) cont rol s the high-impedance state of the mtu?s waveform output pins programmable pulse generator (ppg) ? (4 bits ? 4 groups) ? 1 unit ? pulse output with the mtu output as a trigger ? maximum of 16 pulse-output possible 8-bit timer (tmr) ? (8 bits ? 2 channels) ? 2 units ? select from among seven internal clock signals (pclk/1, pclk/2, pclk/8, pclk/32, pclk/64, pclk/1024, pclk/8192) and one external clock signal ? capable of output of pulse trains wi th desired duty cycles or of pwm signals ? the 2 channels of each unit can be cascaded to create a 16-bit timer ? capable of generating baud-rate clocks for sci5, sci6, and sci12 ? capable of generating a receive clock for the rcr compare match timer (cmt) ? (16 bits ? 2 channels) ? 2 units ? select from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) watchdog timer (wdta) ? 14 bits ? 1 channel ? select from among six counter-input clock signals (pclk/4, pclk/64, pclk/128, pclk/512, pclk/2048, pclk/8192) table 1.1 outline of specifications (2 / 4) classification module/function description
r01ds0255ej0100 rev.1.00 page 4 of 106 feb 25, 2015 RX634 group 1. overview timers independent watchdog timer (iwdta) ? 14 bits ? 1 channel ? counter-input clock: iwdt-dedicated on-chip oscillator frequency divided by 1, 16, 32, 64, 128, or 256 communication functions serial communications interfaces (scie, scif) ? 13 channels (channel 0 to 11: scie, channel 12: scif) ? serial communications modes: asynchronous, clock synchronous, and smart-card interface ? on-chip baud rate generator allows selection of the desired bit rate ? choice of lsb-first or msb-first transfer ? average transfer rate clock can be input fr om tmr timers (sci5, sci6, and sci12) ? simple iic ? simple spi ? master/slave mode supported (scif only) ? start frame and information frame are included (scif only) i 2 c bus interface (riic) ? 3 channel ? communications formats: i 2 c bus format/smbus format ? master/slave selectable ? max. transfer rate: supports the fast mode (400 kbps) serial peripheral interface (rspi) ? 2 channels ? transfer facility using the mosi (master out, slave in), miso (mast er in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock-synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception cec transmission/ reception circuit (cec) (3-v packages only) cec signals can be generated and received conforming to the cec standard, and communication states can be detected by hardware. ? serial communication can be performed conforming to the cec standard. ? the operating clock can be selected from among the pclk, main clock, and iwdtclk. ? any value can be set for the low-level width/bit width of the start bit and data bit during transmission and reception. ? errors and communication states can be detected by hardware. ? an error handling pulse can be output when a timing error of the long bit width is detected. ? signal-free time can be counted. ? receive operation can be restarted by detecting the start bit during reception. remote control signal receiver (rcr) (3-v packages only) ? two units ? four pattern matching (header, data 0, data 1, and special data detection) ? 8-byte receive buffer per unit ? the operating clock can be selected from among the pclk, main clock, iwdtclk, and tmr. 12-bit a/d converter (s12adb) ? 12 bits (16 channels ? 1 unit) ? 12-bit resolution ? minimum conversion time: 1.0 ? s per channel (in operation with adclk at 50 mhz) ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) ? sample-and-hold function ? self-diagnosis for the a/d converter ? assistance in detecting disconnected analog inputs ? double-trigger mode (duplication of a/d conversion data) ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu), an external trigger signal, or elc d/a converter (da) ? 2 channels ? 10-bit resolution ? output voltage: 0 v to vrefh crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. data operation circuit (doc) comparison, addition, and subtraction of 16-bit data operating frequency 54 mhz table 1.1 outline of specifications (3 / 4) classification module/function description
r01ds0255ej0100 rev.1.00 page 5 of 106 feb 25, 2015 RX634 group 1. overview power supply voltage ? 3-v package vcc = avcc0 = vrefh0 = 2.7 to 3.6 v ? 5-v package vcc = avcc0 = vrefh0 = 4.0 to 5.5 v operating temperature ? 40 to +85c (products with wide-temperature-range spec.) packages 144-pin lqfp (plqp0144ka-a) on-chip debugging system ? e1 emulator (jtag and fine interfaces) ? e20 emulator (jtag interface) table 1.1 outline of specifications (4 / 4) classification module/function description
r01ds0255ej0100 rev.1.00 page 6 of 106 feb 25, 2015 RX634 group 1. overview table 1.2 comparison of functions of different RX634 group products functions RX634 group group products 3-v package 5-v package external bus external bus width 16 bits dma dma controller channels 0 to 3 data transfer controller supported timers 16-bit timer pulse unit channels 0 to 5 multi-function timer pulse unit 2 channels 0 to 5 port output enable 2 supported programmable pulse generator supported 8-bit timer channels 0 to 3 compare match timer channels 0 to 3 watchdog timer supported independent watchdog timer supported communication functions serial communications interface (scie) channels 0 to 11 serial communications interface (scif) channel 12 i 2 c bus interface channels 0, 1, 3 serial peripheral interface channels 0, 1 cec transmission/reception circuit (cec) supported not supported remote control signal receiver (rcr) channels 0, 1 not supported 12-bit a/d converter an000 to an015 d/a converter channels 0, 1 crc calculator supported event link controller supported clock frequency accuracy meas urement circuit (cac) supported
r01ds0255ej0100 rev.1.00 page 7 of 106 feb 25, 2015 RX634 group 1. overview 1.2 list of products table 1.3 is a lists of products, and figure 1.1 shows how to read the product part no., memory capacity, and package type. note: orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. figure 1.1 how to read the product part no., memory capacity, and package type table 1.3 list of products group part no. orderable part no. package rom capacity ram capacity power supply voltage RX634 r5f5634eydfb r5f5634eydfb#30 plqp0144ka-a 2 mbytes 128 kbytes vcc = avcc0 = 4.0 to 5.5v r5f5634ecdfb r5f5634ecdfb#30 plqp0144ka-a 2 mbytes 128 kbytes vcc = avcc0 = 2.7 to 3.6v r5f5634dydfb r5f5634dydfb#30 plqp0144ka-a 1.5 mbytes 128 kbytes vcc = avcc0 = 4.0 to 5.5v r5f5634dcdfb r5f5634dcdfb#30 plqp0144ka-a 1.5 mbytes 128 kbytes vcc = avcc0 = 2.7 to 3.6v r5f5634bydfb r5f5634bydfb#30 plqp0144ka-a 1 mbyte 128 kbytes vcc = avcc0 = 4.0 to 5.5v r5f5634bcdfb r5f5634bcdfb#30 plqp0144ka-a 1 mbyte 128 kbytes vcc = avcc0 = 2.7 to 3.6v r5f5634eydfb package type, number of pins, and pin pitch lqfp/144/0.50 d : products with wide-temperature-range spec. ( ? 40 to +85c) y : 5-v package c : 3-v package rom, ram, and e2 dataflash capacity e: 2 mbytes/128 kbytes/32 kbytes d: 1.5 mbytes/128 kbytes/32 kbytes b: 1 mbyte/128 kbytes/32 kbytes group name 34 : RX634 group series name rx600 series type of memory f : flash memory version renesas mcu renesas semiconductor product
r01ds0255ej0100 rev.1.00 page 8 of 106 feb 25, 2015 RX634 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram external bus bsc operand bus instruction bus internal main bus 1 clock generation circuit rx cpu ram rom internal main bus 2 dtca dmaca 4 channels icub e2 dataflash wdta iwdta elc crc tmr 2 channels (unit 1) tmr 2 channels (unit 0) cmt 2 channels (unit 1) cmt 2 channels (unit 0) 12-bit a/d converter 16 channels 10-bit d/a converter 2 channels doc cac tpua 6 channels port l port k port f port h port j port e port a port b port c port d port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 ppg rspi 2 channels riic 3 channels scie 12 channels scif 1 channel mpu mtu2a 6 channels poe2a rcr 2 channels cec internal peripheral buses 1 to 6 cec: cec transmission/reception circuit rcr: remote control signal receiver icub: interrupt controller dtca: data transfer controller dmaca: dma controller bsc: bus controller wdta: watchdog timer iwdta: independent watchdog timer elc: event link controller crc: crc (cyclic redundanc y check) calculator scie, scif: serial communications interface rspi: serial peripheral interface riic: i 2 c bus interface tpua: 16-bit timer pulse unit mtu2a: multi-function timer pulse unit 2 poe2a: port output enable 2 ppg: programmable pulse generator tmr: 8-bit timer cmt: compare match timer doc: data operation circuit cac: clock frequency accuracy measurement circuit
r01ds0255ej0100 rev.1.00 page 9 of 106 feb 25, 2015 RX634 group 1. overview 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1 / 4) classifications pin name i/o description power supply vcc ? power supply pin. connect this pin to the system power supply. connect the pin to vss via a 0.1- f multilayer ceramic capacitor. the capacitor should be pl aced close to the pin. vcl ? connect this pin to the vss pin via the 0.1 f smoothing capacitor used to stabilize the internal power supply. place the capacitor close to the pin. vss ? ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal resonator. an external clock signal can be input through the extal pin. extal input bclk output outputs the external bus clock for external devices. clock frequency accuracy measurement cacref input input for the trigger signal in measuring accura cy of the clock frequency operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. system control res# input reset pin. this mcu enters the reset state when this signal goes low. emle input input pin for the on-chip em ulator enable signal. when the onchip emulator is used, this pin should be driven high. when not used, it should be driven low. on-chip emulator finec input fine interface clock pin fined i/o fine interface pin trst# input on-chip emulator pins. when the emle pin is driven high, these pins are dedicated for the on-chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data. trsync# output this pin indicates that out put from the trdata0 to trdata3 pins is valid. trdata0 to trdata3 output these pi ns output the trace information. address bus a0 to a23 output output pins for the address. data bus d0 to d15 i/o input and output pins for the bidirectional data bus. multiplexed bus a0/d0 to a15/d15 i/o address/data multiplexed bus bus control rd# output strobe signal which indi cates that reading from the external bus interface space is in progress. wr# output strobe signal which indicates that writing to the external bus interface space is in progress, in single-write strobe mode. wr0# to wr1# output strobe signals which indicate that either group of data bus pins (d7 to d0, and d15 to d8) is valid in wr iting to the external bus interface space, in byte strobe mode. bc0# to bc1# output strobe signals which indicate that either group of data bus pins (d7 to d0 and d15 to d8) is valid in access to the external bus interface space, in single-write strobe mode. ale output address latch signal when address/data multiplexed bus is selected. wait# input input pin for wait request sign als in access to the external space. cs0# to cs3# output select signals for areas 0 to 3.
r01ds0255ej0100 rev.1.00 page 10 of 106 feb 25, 2015 RX634 group 1. overview interrupt nmi input non-maskable interrupt request pin. irq0 to irq12 input interrupt request pins. 16-bit timer pulse unit tioca0, tiocb0 tiocc0, tiocd0 i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins. tioca1, tiocb1 i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins. tioca2, tiocb2 i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins. tioca3, tiocb3 tiocc3, tiocd3 i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins. tioca4, tiocb4 i/o the tgra4 and tgrb4 input capture input/output compare output/ pwm output pins. tioca5, tiocb5 i/o the tgra5 and tgrb5 input capture input/output compare output/ pwm output pins. tclka, tclkb tclkc, tclkd input input pins for external clock signals. multi-function timer pulse unit 2 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/ pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. port output enable 2 poe0# to poe3#, poe8# input input pins for request signals to place the mtu pins in the high impedance state. programmable pulse generator po0 to po15 output output pins for the pulse signals. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for external clocks to be input to the counter. tmri0 to tmri3 input input pins for the counter reset. table 1.4 pin functions (2 / 4) classifications pin name i/o description
r01ds0255ej0100 rev.1.00 page 11 of 106 feb 25, 2015 RX634 group 1. overview serial communications interface (scie) ? asynchronous mode/cl ock synchronous mode sck0 to sck11 i/o input/output pins for the clock rxd0 to rxd11 input input pins for received data txd0 to txd11 output output pins for transmitted data cts0# to cts11# input input pins for controll ing the start of transmission and reception rts0# to rts11# output output pins for contro lling the start of transmission and reception ? simple i 2 c mode sscl0 to sscl11 i/o input/output pins for the i 2 c clock ssda0 to ssda11 i/o input/output pins for the i 2 c data ? simple spi mode sck0 to sck11 i/o input/output pins for the clock smiso0 to smiso11 i/o input/output pins for slave transmission of data smosi0 to smosi11 i/o input/output pins for master transmission of data ss0# to ss11# input chip-select input pins serial communications interface (scif) ? asynchronous mode/cl ock synchronous mode sck12 i/o input/output pin for the clock rxd12 input input pin for received data txd12 output output pin for transmitted data cts12# input input pin for controlling t he start of transmission and reception rts12# output output pin for controlling the start of transmission and reception ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock ssda12 i/o input/output pin for the i 2 c data ? simple spi mode sck12 i/o input/output pin for the clock smiso12 i/o input/output pin for slave transmit data smosi12 i/o input/output pin for master transmit data ss12# input chip-select input pin ? extended serial mode rxdx12 input input pin for data reception by scid txdx12 output output pin for data transmission by scid siox12 i/o input/output pin for data reception or transmission by scid i 2 c bus interface scl0, scl1, scl3 i/o input/output pin for i 2 c bus interface clocks . bus can be directly driven by the n-channel open-drain output. sda0, sda1, sda3 i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open-drain output. serial peripheral interface rspcka, rspckb i/o clock input/output pin for the rspi. mosia, mosib i/o input or output data output from the master for the rspi. misoa, misob i/o input or output data output from the slave for the rspi. ssla0, sslb0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 sslb1 to sslb3 output output pins to select the slave for the rspi. cec transmission/ reception circuit (cec) cecio i/o input/output pin for cec communication data remote control signal receiver (rcr) pmc0 input input pin for external pulse signal pmc1 input input pin for external pulse signal table 1.4 pin functions (3 / 4) classifications pin name i/o description
r01ds0255ej0100 rev.1.00 page 12 of 106 feb 25, 2015 RX634 group 1. overview note 1. the p73 pin is avail able only in 5-v packages. it is not available in 3-v packages. note 2. the pl5 pin is avail able only in 3-v packages. it is not available in 5-v packages. 12-bit a/d converter an000 to an015 input input pins for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signals that start the a/d conversion. d/a converter da0, da1 output output pins for t he analog signals to be processed by the d/a converter. analog power supply avcc0 ? analog vo ltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. avss0 ? analog ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh0 ? analog reference voltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. vrefl0 ? analog reference ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh ? analog voltage supply pin for the d/a converter. connect this pin to vcc if the d/a converter is not to be used. vrefl ? analog ground pin for the d/a conv erter. connect this pin to vss if the d/a converter is not to be used. i/o ports p00 to p03, p05, p07 i/o 6-bit input/output pins. p12 to p17 i/o 6-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p35 i/o 6-bit input/output pins. (p35 input pin) p40 to p47 input 8-bit input pins. p50 to p56 i/o 7-bit input/output pins. p60 to p67 i/o 8-bit input/output pins. p70 to p77* 1 i/o 8-bit input/output pins. p80 to p83, p86, p87 i/o 6-bit input/output pins. p90 to p93 i/o 4-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. pf5 i/o 1-bit input/output pin. ph0 to ph3 i/o 4-bit input/output pins. pj1 to pj5 i/o 5-bit input/output pins. pk2 to pk5 i/o 4-bit input/output pins. pl0, pl1, pl5* 2 i/o 3-bit input/output pins. table 1.4 pin functions (4 / 4) classifications pin name i/o description
r01ds0255ej0100 rev.1.00 page 13 of 106 feb 25, 2015 RX634 group 1. overview 1.5 pin assignments figure 1.3 shows the pin assignments. table 1.5 shows the lists of pins and pin functions. figure 1.3 pin assignments of the 144-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0 p64 p63 p62 p61 pk3 p60 pk2 pd7 pd6 pd5 pd4 pd2 pd1 pd0 p93 p92 p91 vss p90 vcc p47 p46 p45 p44 p43 p42 p41 vrefl0 p40 vrefh0 p07 pe1 pd3 avcc0 p74 pc2 p76 p77 pc3 pc4 p80 p81 p82 pc5 pc6 pc7 vcc vss p50 p51 p52 p53 p54 p55 p56 ph0 ph1 ph2 ph3 p12 p13 p14 p15 p86 p16 p87 p20 p75 p83 p17 pe3 pe5 pk4 p70 pk5 pe6 pe7 p65 p66 p67 pa0 pa1 pa2 vss pa4 vcc pa5 pa6 pa7 pb0 p71 p72 pb1 pb2 pb3 pb4 pb5 pb6 pb7 p73/pl5 *1, *2 pl0 pc0 pc1 pe4 pa3 pl1 avss0 vrefh p03 vrefl p02 p01 p00 pf5 emle pj5 vss pj3 vcl md/fined pj2 pj4 res# xtal vss extal vcc p35 p34 p32 p31 p30 p27 p26 p25 p24 p23 p21 p05 pj1 p22 p33 pe2 RX634 group plqp0144ka-a (144-pin lqfp) (top view) note: this figure indicates the power supply pins and i /o port pins. for the pin configuration, see the table ?list of pins and pin functions (144-pin lqfp)?. note 1. the p73 pin is available only in 5-v packages. it is not available in 3-v packages. note 2. the pl5 pin is available only in 3-v packages. it is not available in 5-v packages.
r01ds0255ej0100 rev.1.00 page 14 of 106 feb 25, 2015 RX634 group 1. overview table 1.5 list of pins and pin functions (144-pin lqfp) (1 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, poe, ppg, cac) communications (scie, scif, rspi, riic, cec, rcr) interrupt ad, da 1 avss0 2p 0 5 da1 3vrefh 4p 0 3 irq11 da0 5vrefl 6 p02 tmci1 sck6 irq10 7 p01 tmci0 rxd6/smiso6/sscl6/pmc1 irq9 8 p00 tmri0 txd6/smosi6/ssda6/pmc0 irq8 9p f 5 irq4 10 emle 11 pj5 12 vss 13 pj3 mtioc3c cts0#/rts0#/ss0#/cts6#/ rts6#/ss6# 14 vcl 15 pj1 mtioc3a 16 md/fined 17 pj2 18 pj4 19 res# 20 xtal 21 vss 22 extal 23 vcc 24 p35 nmi 25 trst# p34 mtioc0a/tmci3/poe2#/ po12 sck0/sck6 irq4 26 p33 mtioc0d/tiocd0/tmri3/ poe3#/po11 rxd0/smiso0/sscl0/rxd6/ smiso6/sscl6 irq3_ds 27 p32 mtioc0c/tiocc0/tmo3/ po10 txd0/smosi0/ssda0/txd6/ smosi6/ssda6 irq2_ds 28 tms p31 mtioc4d/tmci2/po9 cts1#/rts1#/ss1#/sslb0 irq1_ds 29 tdi p30 mtioc4b/tmri3/poe8#/ po8 rxd1/smiso1/sscl1/misob irq0_ds 30 finec/tck p27 cs3# mtioc2 b/tmci3/po7 sck1/rspckb 31 tdo p26 cs2# mtioc2a/tmo1/po6 txd1/smosi1/ssda1/cts3#/ rts3#/ss3#/mosib 32 p25 cs1# mtioc4c/mtclkb/tioca4/ po5 rxd3/smiso3/sscl3 adtrg0# 33 p24 cs0# mtioc4a/mtclka/tiocb4/ tmri1/po4 sck3 34 p23 mtioc3d/mtclkd/ tiocd3/po3 txd3/smosi3/ssda3/cts0#/ rts0#/ss0# 35 p22 mtioc3b/mtclkc/tiocc3/ tmo0/po2 sck0 36 p21 mtioc1b/tioca3/tmci0/ po1 rxd0/smiso0/sscl0/scl1 irq9 37 p20 mtioc1a/tiocb3/tmri0/ po0 txd0/smosi0/ssda0/sda1 irq8 38 p17 mtioc3a/mtioc3b/ tiocb0/tclkd/tmo1/ poe8#/po15 sck1/txd3/smosi3/ssda3/ misoa/sda0_ds irq7
r01ds0255ej0100 rev.1.00 page 15 of 106 feb 25, 2015 RX634 group 1. overview 39 p87 tioca2 40 p16 mtioc3c/mtioc3d/ tiocb1/tclkc/tmo2/po14 txd1/smosi1/ssda1/rxd3/ smiso3/sscl3/mosia/ scl0_ds irq6 adtrg0# 41 p86 tioca0 42 p15 mtioc0b/mtclkb/tiocb2/ tclkb/tmci2/po13 rxd1/smiso1/sscl1/sck3 irq5 43 p14 mtioc3a/mtclka/tiocb5/ tclka/tmri2/po15 cts1#/rts1#/ss1# irq4 44 p13 mtioc0b/tioca5/tmo3/ po13 txd2/smosi2/ssda2/sda0 irq3 45 p12 tmci1 rxd2/smiso2/sscl2/scl0 irq2 46 ph3 tmci0 47 ph2 tmri0 irq1 48 ph1 tmo0 irq0 49 ph0 cacref 50 p56 mtioc3c/tioca1 51 trdata3 p55 wait# mtioc4d/tmo3 irq10 52 trdata2 p54 ale mtioc4b/tmci1 cts2#/rts2#/ss2# 53 p53 bclk 54 p52 rd# rxd2/smiso2/sscl2/sslb3 55 p51 wr1#/bc1#/ wait# sck2/sslb2 56 p50 wr0#/wr# txd2/smosi2/ssda2/sslb1 57 vss 58 trclk p83 mtioc4c cts10#/rts10#/ss10# 59 vcc 60 pc7 a23/cs0# mtioc3a/mtclkb/tmo2/ cacref txd8/smosi8/ssda8/misoa 61 pc6 a22/cs1# mtioc3c/mtclka/t mci2 rxd8/smiso8/sscl8/mosia 62 pc5 a21/cs2#/ wait# mtioc3b/mtclkd/tmri2 sck8/rspcka 63 trsync# p82 mtioc4a txd10/smosi10/ssda10 64 trdata1 p81 mtioc3d rxd10/smiso10/sscl10 65 trdata0 p80 mtioc3b sck10 66 pc4 a20/cs3# mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 67 pc3 a19 mtioc4d/tclkb txd5/smosi5/ssda5 68 p77 txd11/smosi11/ssda11 69 p76 rxd11/smiso11/sscl11 70 pc2 a18 mtioc4b/tclka rxd5/smiso5/sscl5/ssla3 71 p75 sck11 72 p74 cts11#/rts11#/ss11# 73 pc1 a17 mtioc3a/tclkd sck5/ssla2/sda3 irq12 74 pl1 75 pc0 a16 mtioc3c/tclkc cts5#/rts5#/ss5#/ssla1/ scl3 76 pl0 77 p73* 1 irq12 pl5* 1 cecio irq12 78 pb7 a15 mtioc3b/tiocb5 txd9/smosi9/ssda9 table 1.5 list of pins and pin functions (144-pin lqfp) (2 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, poe, ppg, cac) communications (scie, scif, rspi, riic, cec, rcr) interrupt ad, da
r01ds0255ej0100 rev.1.00 page 16 of 106 feb 25, 2015 RX634 group 1. overview 79 pb6 a14 mtioc3d/tioca5 rxd9/smiso9/sscl9 80 pb5 a13 mtioc2a/mtioc1b/ tiocb4/tmri1/poe1# sck9 81 pb4 a12 tioca4 cts9#/rts9#/ss9# 82 pb3 a11 mtioc0a/mtioc4a/ tiocd3/tclkd/tmo0/ poe3# sck4/sck6 83 pb2 a10 tiocc3/tclkc cts4#/rts4#/ss4#/cts6#/ rts6#/ss6# 84 pb1 a9 mtioc0c/mtioc4c/ tiocb3/tmci0 txd4/smosi4/ssda4/txd6/ smosi6/ssda6 irq4_ds 85 p72 86 p71 87 pb0 a8 mtic5w/tioca3 rxd4/smiso4/sscl4/rxd6/ smiso6/sscl6/rspcka irq12 88 pa7 a7 tiocb2 misoa 89 pa6 a6 mtic5v/mtclkb/tioca2/ tmci3/poe2# cts5#/rts5#/ss5#/mosia 90 pa5 a5 tiocb1 rspcka 91 vcc 92 pa4 a4 mtic5u/mtclka/tioca1/ tmri0 txd5/smosi5/ssda5/ssla0 irq5_ds 93 vss 94 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb rxd5/smiso5/sscl5 irq6_ds 95 pa2 a2 rxd5/smiso5/sscl5/ssla3 96 pa1 a1 mtioc0b/mtclkc/tiocb0 sck5/ssla2 irq11 97 pa0 a0/bc0# mtioc4a/tioca0/cacref ssla1 98 p67 99 p66 100 p65 101 pe7 d15 [a15/d15] misob irq7 an015 102 pe6 d14 [a14/d14] cts4#/rts4#/ss4#/mosib irq6 an014 103 pk5 txd4/smosi4/ssda4 104 p70 sck4 105 pk4 rxd4/smiso4/sscl4 106 pe5 d13 [a13/d13] mtioc4c/mtioc2b rspckb irq5 an013 107 pe4 d12 [a12/d12] mtioc4d/mtioc1a sslb0 an012 108 pe3 d11 [a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12#/ misob an011 109 pe2 d10 [a10/d10] mtioc4a rxd12/rxdx12/smiso12/ sscl12/sslb3/mosib irq7_ds an010 110 pe1 d9 [a9/d9] mtioc4c txd12/txdx12/smosi12/ ssda12/sslb2/rspckb/ siox12 an009 111 pe0 d8 [a8/d8] sck12/sslb1 an008 112 p64 113 p63 114 p62 115 p61 cts9#/rts9#/ss9# 116 pk3 rxd9/smiso9/sscl9 117 p60 sck9 table 1.5 list of pins and pin functions (144-pin lqfp) (3 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, poe, ppg, cac) communications (scie, scif, rspi, riic, cec, rcr) interrupt ad, da
r01ds0255ej0100 rev.1.00 page 17 of 106 feb 25, 2015 RX634 group 1. overview note 1. pin 77 is available as p73 in 5-v packages, and pl5 in 3-v packages. 118 pk2 txd9/smosi9/ssda9 119 pd7 d7 [a7/d7] mtic5u/poe0# irq7 120 pd6 d6 [a6/d6] mtic5v/poe1# irq6 121 pd5 d5 [a5/d5] mtic5w/poe2# irq5 122 pd4 d4 [a4/d4] poe3# irq4 123 pd3 d3 [a3/d3] poe8# irq3 124 pd2 d2 [a2/d2] mtioc4d irq2 125 pd1 d1 [a1/d1] mtioc4b irq1 126 pd0 d0 [a0/d0] irq0 127 p93 cts7#/rts7#/ss7# 128 p92 rxd7/smiso7/sscl7 129 p91 sck7 130 vss 131 p90 txd7/smosi7/ssda7 132 vcc 133 p47 an007 134 p46 an006 135 p45 an005 136 p44 an004 137 p43 an003 138 p42 an002 139 p41 an001 140 vrefl0 141 p40 an000 142 vrefh0 143 avcc0 144 p07 adtrg0# table 1.5 list of pins and pin functions (144-pin lqfp) (4 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tpu, tmr, poe, ppg, cac) communications (scie, scif, rspi, riic, cec, rcr) interrupt ad, da
r01ds0255ej0100 rev.1.00 page 18 of 106 feb 25, 2015 RX634 group 2. cpu 2. cpu figure 2.1 shows the register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp)* 1 general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0255ej0100 rev.1.00 page 19 of 106 feb 25, 2015 RX634 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. (8) floating-point status word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (e j) enables the exception handling (ej = 1) , the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if th e exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v).
r01ds0255ej0100 rev.1.00 page 20 of 106 feb 25, 2015 RX634 group 2. cpu 2.3 register associated with dsp instructions (1) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instructions. the accumula tor is also used for the multiply and multiply-and-accumulate instructions; em ul, emulu, fmul, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0255ej0100 rev.1.00 page 21 of 106 feb 25, 2015 RX634 group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and states of control bits.
r01ds0255ej0100 rev.1.00 page 22 of 106 feb 25, 2015 RX634 group 3. address space figure 3.1 memory map in each operating mode reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 reserved area *3 on-chip rom (e2dataflash) (32 kb) reserved area *3 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 ram on-chip rom (program rom) *2 (read only) 0010 0000h peripheral i/o registers 0010 8000h 0080 0000h 0100 0000h on-chip rom (program rom) *2 (write only) ffe0 0000h ff7f c000h on-chip rom (user boot) (read only) (16 kb) peripheral i/o registers peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode ram on-chip rom (program rom) *2 (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (e2dataflash) (32 kb) 0080 0000h 0100 0000h on-chip rom (program rom) *2 (write only) 0800 0000h ffe0 0000h ff7f c000h on-chip rom (user boot) (read only) (16 kb) peripheral i/o registers peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0002 0000h external address space 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode ram 0010 0000h peripheral i/o registers 0800 0000h ff00 0000h 0002 0000h external address space ff80 0000h ff80 0000h 00e0 0000h 00e0 0000h 0500 0000h external address space 0500 0000h note 1. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. note 2. the rom capacity differs depending on the products. note: see table 1.3, list of products, for the product type name. note 3. reserved areas should not be accessed. rom (byte) ram (byte) capacity address (for reading) address (for writing) capacity address 2 m ffe0 0000h to ffff ffffh 00e0 0000h to 00ff ffffh 128 k 0000 0000h to 0001 ffffh 1.5 m ffe8 0000h to ffff ffffh 00e8 0000h to 00ff ffffh 128 k 0000 0000h to 0001 ffffh 1 m fff0 0000h to ffff ffffh 00f0 0000h to 00ff ffffh 128 k 0000 0000h to 0001 ffffh
r01ds0255ej0100 rev.1.00 page 23 of 106 feb 25, 2015 RX634 group 3. address space 3.2 external address space the external address space is divided into up to four cs areas (cs0 to cs3) , each corresponding to the csn# signal output from a csn# (n = 0 to 3) pin. figure 3.2 shows the address ranges corresponding to the indivi dual cs areas (cs0 to cs3) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces and cs areas (in on-chip rom disabl ed extended mode) 0500 0000h 0600 0000h 0700 0000h cs3 (16 mb) 05ff ffffh 06ff ffffh 07ff ffffh cs2 (16 mb) cs1 (16 mb) ffff ffffh ff00 0000h cs0 (16 mb) note 1. reserved areas should not be accessed. note 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the address space for addresses above 0800 0000h is as shown in figure on this section ?memory map in each operating mode?. reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode on-chip ram 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h 0002 0000h external address space* 2 external address space 0500 0000h
r01ds0255ej0100 rev.1.00 page 24 of 106 feb 25, 2015 RX634 group 4. i/o registers 4. i/o registers this section gives information on the on-chip i/o register addr esses. the information is given as shown below. notes on writing to registers are also given at the end. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? the number of access cycles indicates the number of cycles based on the specified reference clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o re gister, the cpu starts executing the subsequent in struction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0255ej0100 rev.1.00 page 25 of 106 feb 25, 2015 RX634 group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for the number of i/o regist er access cycles, refer to table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. *1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral buses 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 or registers for the ex ternal bus control unit (except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk, bclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access states shown in table 4.1. when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. in the external bus control unit, the sum of the number of bu s cycles for internal main bus 1 and the number of divided clock synchronization cycles will be one cycle of bclk at a maximum. therefore, one bclk is added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access fr om the cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dmac or dtc).
r01ds0255ej0100 rev.1.00 page 26 of 106 feb 25, 2015 RX634 group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk operating modes 0008 0002h system mode status register mdsr 16 16 3 iclk 0008 0006h system system control register 0 syscr0 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk low power consumption 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk clock generation circuit 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0030h system external bus clock control register bckcr 8 8 3 iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0034h system low-speed on-chip oscillator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk low power consumption 0008 00a1h system sleep mode return clock source switching register rstckcr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register moscwtcr 8 8 3 iclk 0008 00a6h system pll wait control register pllwtcr 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk resets 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit control register 1 lvd1cr1 8 8 3 iclk lvda 0008 00e1h system voltage monitoring 1 circuit status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk register write protection function 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk buses 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk dmaca 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk
r01ds0255ej0100 rev.1.00 page 27 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk dmaca 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk 0008 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dma module activation register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk dtca 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 3002h bsc cs0 mode register cs0mod 16 16 1 to 2bclk buses 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1 to 2bclk 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1 to 2bclk 0008 3012h bsc cs1 mode register cs1mod 16 16 1 to 2bclk 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1 to 2bclk 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1 to 2bclk table 4.1 list of i/o register s (address order) (2 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 28 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 3022h bsc cs2 mode register cs2mod 16 16 1 to 2bclk buses 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1 to 2bclk 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1 to 2bclk 0008 3032h bsc cs3 mode register cs3mod 16 16 1 to 2bclk 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1 to 2bclk 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1 to 2bclk 0008 3802h bsc cs0 control register cs0cr 16 16 1 to 2bclk 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1 to 2bclk 0008 3812h bsc cs1 control register cs1cr 16 16 1 to 2bclk 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1 to 2bclk 0008 3822h bsc cs2 control register cs2cr 16 16 1 to 2bclk 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1 to 2bclk 0008 3832h bsc cs3 control register cs3cr 16 16 1 to 2bclk 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1 to 2bclk 0008 3880h bsc cs recovery cycle insertion enable register csrecen 16 16 1 to 2bclk 0008 6400h mpu region-0 start page number register rspage0 32 32 1 iclk mpu 0008 6404h mpu region-0 end page number register repage0 32 32 1 iclk 0008 6408h mpu region-1 start page number register rspage1 32 32 1 iclk 0008 640ch mpu region-1 end page number register repage1 32 32 1 iclk 0008 6410h mpu region-2 start page number register rspage2 32 32 1 iclk 0008 6414h mpu region-2 end page number register repage2 32 32 1 iclk 0008 6418h mpu region-3 start page number register rspage3 32 32 1 iclk 0008 641ch mpu region-3 end page number register repage3 32 32 1 iclk 0008 6420h mpu region-4 start page number register rspage4 32 32 1 iclk 0008 6424h mpu region-4 end page number register repage4 32 32 1 iclk 0008 6428h mpu region-5 start page number register rspage5 32 32 1 iclk 0008 642ch mpu region-5 end page number register repage5 32 32 1 iclk 0008 6430h mpu region-6 start page number register rspage6 32 32 1 iclk 0008 6434h mpu region-6 end page number register repage6 32 32 1 iclk 0008 6438h mpu region-7 start page number register rspage7 32 32 1 iclk 0008 643ch mpu region-7 end page number register repage7 32 32 1 iclk 0008 6500h mpu memory-protection enable register mpen 32 32 1 iclk 0008 6504h mpu background access control register mpbac 32 32 1 iclk 0008 6508h mpu memory-protection error status-clearing register mpeclr 32 32 1 iclk 0008 650ch mpu memory-protection error status register mpests 32 32 1 iclk 0008 6514h mpu data memory-protection error address register mpdea 32 32 1 iclk 0008 6520h mpu region search address register mpsa 32 32 1 iclk 0008 6524h mpu region search operation register mpops 16 16 1 iclk 0008 6526h mpu region invalidation operation register mpopi 16 16 1 iclk 0008 6528h mpu instruction-hit region register mhiti 32 32 1 iclk 0008 652ch mpu data-hit region register mhitd 32 32 1 iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk icub 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk table 4.1 list of i/o register s (address order) (3 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 29 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk icub 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7030h icu interrupt request register 048 ir048 8 8 2 iclk 0008 7031h icu interrupt request register 049 ir049 8 8 2 iclk 0008 7032h icu interrupt request register 050 ir050 8 8 2 iclk 0008 7033h icu interrupt request register 051 ir051 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7048h icu interrupt request register 072 ir072 8 8 2 iclk 0008 7049h icu interrupt request register 073 ir073 8 8 2 iclk 0008 704ah icu interrupt request register 074 ir074 8 8 2 iclk 0008 704bh icu interrupt request register 075 ir075 8 8 2 iclk 0008 704ch icu interrupt request register 076 ir076 8 8 2 iclk 0008 704dh icu interrupt request register 077 ir077 8 8 2 iclk not available in 5-v packages. 0008 704eh icu interrupt request register 078 ir078 8 8 2 iclk not available in 5-v packages. 0008 704fh icu interrupt request register 079 ir079 8 8 2 iclk not available in 5-v packages. 0008 705eh icu interrupt request register 094 ir094 8 8 2 iclk not available in 5-v packages. 0008 705fh icu interrupt request register 095 ir095 8 8 2 iclk not available in 5-v packages. 0008 7062h icu interrupt request register 098 ir098 8 8 2 iclk 0008 7063h icu interrupt request register 099 ir099 8 8 2 iclk 0008 7064h icu interrupt request register 100 ir100 8 8 2 iclk 0008 7065h icu interrupt request register 101 ir101 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706bh icu interrupt request register 107 ir107 8 8 2 iclk 0008 706fh icu interrupt request register 111 ir111 8 8 2 iclk not available in 5-v packages. 0008 7070h icu interrupt request register 112 ir112 8 8 2 iclk not available in 5-v packages. 0008 7071h icu interrupt request register 113 ir113 8 8 2 iclk not available in 5-v packages. 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk table 4.1 list of i/o register s (address order) (4 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 30 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk icub 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk 0008 708fh icu interrupt request register 143 ir143 8 8 2 iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7093h icu interrupt request register 147 ir147 8 8 2 iclk 0008 7094h icu interrupt request register 148 ir148 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk 0008 7099h icu interrupt request register 153 ir153 8 8 2 iclk 0008 709ah icu interrupt request register 154 ir154 8 8 2 iclk 0008 709bh icu interrupt request register 155 ir155 8 8 2 iclk 0008 709ch icu interrupt request register 156 ir156 8 8 2 iclk 0008 709dh icu interrupt request register 157 ir157 8 8 2 iclk 0008 709eh icu interrupt request register 158 ir158 8 8 2 iclk 0008 709fh icu interrupt request register 159 ir159 8 8 2 iclk 0008 70a0h icu interrupt request register 160 ir160 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a3h icu interrupt request register 163 ir163 8 8 2 iclk 0008 70a4h icu interrupt request register 164 ir164 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a6h icu interrupt request register 166 ir166 8 8 2 iclk table 4.1 list of i/o register s (address order) (5 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 31 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 70a7h icu interrupt request register 167 ir167 8 8 2 iclk icub 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70bah icu interrupt request register 186 ir186 8 8 2 iclk 0008 70bbh icu interrupt request register 187 ir187 8 8 2 iclk 0008 70bch icu interrupt request register 188 ir188 8 8 2 iclk 0008 70bdh icu interrupt request register 189 ir189 8 8 2 iclk 0008 70beh icu interrupt request register 190 ir190 8 8 2 iclk 0008 70bfh icu interrupt request register 191 ir191 8 8 2 iclk 0008 70c0h icu interrupt request register 192 ir192 8 8 2 iclk 0008 70c1h icu interrupt request register 193 ir193 8 8 2 iclk 0008 70c2h icu interrupt request register 194 ir194 8 8 2 iclk 0008 70c3h icu interrupt request register 195 ir195 8 8 2 iclk 0008 70c4h icu interrupt request register 196 ir196 8 8 2 iclk 0008 70c5h icu interrupt request register 197 ir197 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70cah icu interrupt request register 202 ir202 8 8 2 iclk 0008 70cbh icu interrupt request register 203 ir203 8 8 2 iclk 0008 70cch icu interrupt request register 204 ir204 8 8 2 iclk 0008 70cdh icu interrupt request register 205 ir205 8 8 2 iclk 0008 70ceh icu interrupt request register 206 ir206 8 8 2 iclk 0008 70cfh icu interrupt request register 207 ir207 8 8 2 iclk 0008 70d0h icu interrupt request register 208 ir208 8 8 2 iclk 0008 70d1h icu interrupt request register 209 ir209 8 8 2 iclk 0008 70d2h icu interrupt request register 210 ir210 8 8 2 iclk 0008 70d3h icu interrupt request register 211 ir211 8 8 2 iclk 0008 70d4h icu interrupt request register 212 ir212 8 8 2 iclk 0008 70d5h icu interrupt request register 213 ir213 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk table 4.1 list of i/o register s (address order) (6 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 32 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk icub 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 70fah icu interrupt request register 250 ir250 8 8 2 iclk 0008 70fbh icu interrupt request register 251 ir251 8 8 2 iclk 0008 70fch icu interrupt request register 252 ir252 8 8 2 iclk 0008 70fdh icu interrupt request register 253 ir253 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 7131h icu dtc activation enable register 049 dtcer049 8 8 2 iclk 0008 7132h icu dtc activation enable register 050 dtcer050 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk 0008 7148h icu dtc activation enable register 072 dtcer072 8 8 2 iclk 0008 7149h icu dtc activation enable register 073 dtcer073 8 8 2 iclk table 4.1 list of i/o register s (address order) (7 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 33 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 714ah icu dtc activation enable register 074 dtcer074 8 8 2 iclk icub 0008 714bh icu dtc activation enable register 075 dtcer075 8 8 2 iclk 0008 714ch icu dtc activation enable register 076 dtcer076 8 8 2 iclk 0008 714dh icu dtc activation enable register 077 dtcer077 8 8 2 iclk not available in 5-v packages. 0008 714eh icu dtc activation enable register 078 dtcer078 8 8 2 iclk not available in 5-v packages. 0008 714fh icu dtc activation enable register 079 dtcer079 8 8 2 iclk not available in 5-v packages. 0008 7163h icu dtc activation enable register 099 dtcer099 8 8 2 iclk 0008 7164h icu dtc activation enable register 100 dtcer100 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 716ah icu dtc activation enable register 106 dtcer106 8 8 2 iclk 0008 716bh icu dtc activation enable register 107 dtcer107 8 8 2 iclk 0008 716fh icu dtc activation enable register 111 dtcer111 8 8 2 iclk not available in 5-v packages. 0008 7170h icu dtc activation enable register 112 dtcer112 8 8 2 iclk not available in 5-v packages. 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 718eh icu dtc activation enable register 142 dtcer142 8 8 2 iclk 0008 718fh icu dtc activation enable register 143 dtcer143 8 8 2 iclk 0008 7190h icu dtc activation enable register 144 dtcer144 8 8 2 iclk 0008 7191h icu dtc activation enable register 145 dtcer145 8 8 2 iclk 0008 7193h icu dtc activation enable register 147 dtcer147 8 8 2 iclk 0008 7194h icu dtc activation enable register 148 dtcer148 8 8 2 iclk 0008 7197h icu dtc activation enable register 151 dtcer151 8 8 2 iclk 0008 7198h icu dtc activation enable register 152 dtcer152 8 8 2 iclk 0008 719bh icu dtc activation enable register 155 dtcer155 8 8 2 iclk 0008 719ch icu dtc activation enable register 156 dtcer156 8 8 2 iclk 0008 719dh icu dtc activation enable register 157 dtcer157 8 8 2 iclk 0008 719eh icu dtc activation enable register 158 dtcer158 8 8 2 iclk table 4.1 list of i/o register s (address order) (8 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 34 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 71a0h icu dtc activation enable register 160 dtcer160 8 8 2 iclk icub 0008 71a1h icu dtc activation enable register 161 dtcer161 8 8 2 iclk 0008 71a4h icu dtc activation enable register 164 dtcer164 8 8 2 iclk 0008 71a5h icu dtc activation enable register 165 dtcer165 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71bbh icu dtc activation enable register 187 dtcer187 8 8 2 iclk 0008 71bch icu dtc activation enable register 188 dtcer188 8 8 2 iclk 0008 71bfh icu dtc activation enable register 191 dtcer191 8 8 2 iclk 0008 71c0h icu dtc activation enable register 192 dtcer192 8 8 2 iclk 0008 71c3h icu dtc activation enable register 195 dtcer195 8 8 2 iclk 0008 71c4h icu dtc activation enable register 196 dtcer196 8 8 2 iclk 0008 71c6h icu dtc activation enable register 198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register 199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register 200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register 201 dtcer201 8 8 2 iclk 0008 71cbh icu dtc activation enable register 203 dtcer203 8 8 2 iclk 0008 71cch icu dtc activation enable register 204 dtcer204 8 8 2 iclk 0008 71cfh icu dtc activation enable register 207 dtcer207 8 8 2 iclk 0008 71d0h icu dtc activation enable register 208 dtcer208 8 8 2 iclk 0008 71d3h icu dtc activation enable register 211 dtcer211 8 8 2 iclk 0008 71d4h icu dtc activation enable register 212 dtcer212 8 8 2 iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2 iclk 0008 71d8h icu dtc activation enable register 216 dtcer216 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71e7h icu dtc activation enable register 231 dtcer231 8 8 2 iclk 0008 71e8h icu dtc activation enable register 232 dtcer232 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 71fbh icu dtc activation enable register 251 dtcer251 8 8 2 iclk 0008 71fch icu dtc activation enable register 252 dtcer252 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7206h icu interrupt request enable register 06 ier06 8 8 2 iclk table 4.1 list of i/o register s (address order) (9 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 35 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk icub 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 7209h icu interrupt request enable register 09 ier09 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt ac tivation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk 0008 7301h icu interrupt source priority register 001 ipr001 8 8 2 iclk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 iclk 0008 7330h icu interrupt source priority register 048 ipr048 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 iclk 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 iclk 0008 7348h icu interrupt source priority register 072 ipr072 8 8 2 iclk 0008 7349h icu interrupt source priority register 073 ipr073 8 8 2 iclk 0008 734ah icu interrupt source priority register 074 ipr074 8 8 2 iclk table 4.1 list of i/o register s (address order) (10 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 36 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 734bh icu interrupt source priority register 075 ipr075 8 8 2 iclk icub 0008 734ch icu interrupt source priority register 076 ipr076 8 8 2 iclk 0008 734dh icu interrupt source priority register 077 ipr077 8 8 2 iclk not available in 5-v packages. 0008 734eh icu interrupt source priority register 078 ipr078 8 8 2 iclk not available in 5-v packages. 0008 734fh icu interrupt source priority register 079 ipr079 8 8 2 iclk not available in 5-v packages. 0008 735eh icu interrupt source priority register 094 ipr094 8 8 2 iclk not available in 5-v packages. 0008 735fh icu interrupt source priority register 095 ipr095 8 8 2 iclk not available in 5-v packages. 0008 7362h icu interrupt source priority register 098 ipr098 8 8 2 iclk 0008 7363h icu interrupt source priority register 099 ipr099 8 8 2 iclk 0008 7364h icu interrupt source priority register 100 ipr100 8 8 2 iclk 0008 7365h icu interrupt source priority register 101 ipr101 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 iclk 0008 736bh icu interrupt source priority register 107 ipr107 8 8 2 iclk 0008 736fh icu interrupt source priority register 111 ipr111 8 8 2 iclk not available in 5-v packages. 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 iclk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 iclk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 iclk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 iclk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 iclk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 iclk 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 iclk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk 0008 738eh icu interrupt source priority register 142 ipr142 8 8 2 iclk 0008 7392h icu interrupt source priority register 146 ipr146 8 8 2 iclk 0008 7393h icu interrupt source priority register 147 ipr147 8 8 2 iclk 0008 7395h icu interrupt source priority register 149 ipr149 8 8 2 iclk 0008 7397h icu interrupt source priority register 151 ipr151 8 8 2 iclk 0008 7399h icu interrupt source priority register 153 ipr153 8 8 2 iclk 0008 739bh icu interrupt source priority register 155 ipr155 8 8 2 iclk 0008 739fh icu interrupt source priority register 159 ipr159 8 8 2 iclk 0008 73a0h icu interrupt source priority register 160 ipr160 8 8 2 iclk 0008 73a2h icu interrupt source priority register 162 ipr162 8 8 2 iclk 0008 73a4h icu interrupt source priority register 164 ipr164 8 8 2 iclk 0008 73a6h icu interrupt source priority register 166 ipr166 8 8 2 iclk 0008 73aah icu interrupt source priority register 170 ipr170 8 8 2 iclk 0008 73abh icu interrupt source priority register 171 ipr171 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk table 4.1 list of i/o register s (address order) (11 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 37 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 73bah icu interrupt source priority register 186 ipr186 8 8 2 iclk icub 0008 73beh icu interrupt source priority register 190 ipr190 8 8 2 iclk 0008 73c2h icu interrupt source priority register 194 ipr194 8 8 2 iclk 0008 73c6h icu interrupt source priority register 198 ipr198 8 8 2 iclk 0008 73c7h icu interrupt source priority register 199 ipr199 8 8 2 iclk 0008 73c8h icu interrupt source priority register 200 ipr200 8 8 2 iclk 0008 73c9h icu interrupt source priority register 201 ipr201 8 8 2 iclk 0008 73cah icu interrupt source priority register 202 ipr202 8 8 2 iclk 0008 73cbh icu interrupt source priority register 203 ipr203 8 8 2 iclk 0008 73cch icu interrupt source priority register 204 ipr204 8 8 2 iclk 0008 73cdh icu interrupt source priority register 205 ipr205 8 8 2 iclk 0008 73ceh icu interrupt source priority register 206 ipr206 8 8 2 iclk 0008 73d2h icu interrupt source priority register 210 ipr210 8 8 2 iclk 0008 73d6h icu interrupt source priority register 214 ipr214 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 iclk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 iclk 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 iclk 0008 73e6h icu interrupt source priority register 230 ipr230 8 8 2 iclk 0008 73eah icu interrupt source priority register 234 ipr234 8 8 2 iclk 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 2 iclk 0008 73f2h icu interrupt source priority register 242 ipr242 8 8 2 iclk 0008 73f3h icu interrupt source priority register 243 ipr243 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 2 iclk 0008 73f5h icu interrupt source priority register 245 ipr245 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 iclk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 iclk 0008 73fah icu interrupt source priority register 250 ipr250 8 8 2 iclk 0008 7400h icu dmac activation request select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmac activation request select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmac activation request select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmac activation request select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7508h icu irq control register 8 irqcr8 8 8 2 iclk 0008 7509h icu irq control register 9 irqcr9 8 8 2 iclk 0008 750ah icu irq control r egister 10 irqcr10 8 8 2 iclk 0008 750bh icu irq control register 11 irqcr11 8 8 2 iclk 0008 750ch icu irq control r egister 12 irqcr12 8 8 2 iclk 0008 750dh cec cec interrupt control register 1 cecintcr1 8 8 2 iclk cec not available in 5-v packages. table 4.1 list of i/o register s (address order) (12 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 38 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 750eh cec cec interrupt control register 2 cecintcr2 8 8 2 iclk cec not available in 5-v packages. 0008 750fh cec cec interrupt control register 3 cecintcr3 8 8 2 iclk not available in 5-v packages. 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk icub 0008 7511h icu irq pin digital filter enable register 1 irqflte1 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7516h icu irq pin digital filter setting register 1 irqfltc1 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 to 3pclkb 2 iclk cmt 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 to 3pclkb 2 iclk 0008 8004h cmt0 compare match counter cmcnt 16 16 2 to 3pclkb 2 iclk 0008 8006h cmt0 compare match constant register cmcor 16 16 2 to 3pclkb 2 iclk 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 to 3pclkb 2 iclk 0008 800ah cmt1 compare match counter cmcnt 16 16 2 to 3pclkb 2 iclk 0008 800ch cmt1 compare match constant register cmcor 16 16 2 to 3pclkb 2 iclk 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2 to 3pclkb 2 iclk 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 to 3pclkb 2 iclk 0008 8014h cmt2 compare match counter cmcnt 16 16 2 to 3pclkb 2 iclk 0008 8016h cmt2 compare match constant register cmcor 16 16 2 to 3pclkb 2 iclk 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 to 3pclkb 2 iclk 0008 801ah cmt3 compare match counter cmcnt 16 16 2 to 3pclkb 2 iclk 0008 801ch cmt3 compare match constant register cmcor 16 16 2 to 3pclkb 2 iclk 0008 8020h wdt wdt refresh register wdtrr 8 8 2 to 3pclkb 2 iclk wdta 0008 8022h wdt wdt control register wdtcr 16 16 2 to 3pclkb 2 iclk 0008 8024h wdt wdt status register wdtsr 16 16 2 to 3pclkb 2 iclk 0008 8026h wdt wdt reset control register wdtrcr 8 8 2 to 3pclkb 2 iclk 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 to 3pclkb 2 iclk iwdta 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 to 3pclkb 2 iclk 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 to 3pclkb 2 iclk 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2 to 3pclkb 2 iclk 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2 to 3pclkb 2 iclk 0008 80c0h da d/a data register 0 dadr0 16 16 2 to 3pclkb 2 iclk daa 0008 80c2h da d/a data register 1 dadr1 16 16 2 to 3pclkb 2 iclk 0008 80c4h da d/a control register dacr 8 8 2 to 3pclkb 2 iclk 0008 80c5h da dadrm format select register dadpr 8 8 2 to 3pclkb 2 iclk 0008 8100h tpu timer start register tstr 8 8 2 to 3pclkb 2 iclk tpua 0008 8101h tpu timer synchronous register tsyr 8 8 2 to 3pclkb 2 iclk 0008 8108h tpu0 noise filter control register nfcr 8 8 2 to 3pclkb 2 iclk 0008 8109h tpu1 noise filter control register nfcr 8 8 2 to 3pclkb 2 iclk 0008 810ah tpu2 noise filter control register nfcr 8 8 2 to 3pclkb 2 iclk 0008 810bh tpu3 noise filter control register nfcr 8 8 2 to 3pclkb 2 iclk 0008 810ch tpu4 noise filter control register nfcr 8 8 2 to 3pclkb 2 iclk 0008 810dh tpu5 noise filter control register nfcr 8 8 2 to 3pclkb 2 iclk 0008 8110h tpu0 timer control register tcr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (13 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 39 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 8111h tpu0 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk tpua 0008 8112h tpu0 timer i/o control register h tiorh 8 8 2 to 3pclkb 2 iclk 0008 8113h tpu0 timer i/o control register l tiorl 8 8 2 to 3pclkb 2 iclk 0008 8114h tpu0 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8115h tpu0 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8116h tpu0 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8118h tpu0 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 811ah tpu0 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 811ch tpu0 timer general register c tgrc 16 16 2 to 3pclkb 2 iclk 0008 811eh tpu0 timer general register d tgrd 16 16 2 to 3pclkb 2 iclk 0008 8120h tpu1 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8121h tpu1 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8122h tpu1 timer i/o control register tior 8 8 2 to 3pclkb 2 iclk 0008 8124h tpu1 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8125h tpu1 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8126h tpu1 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8128h tpu1 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 812ah tpu1 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 8130h tpu2 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8131h tpu2 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8132h tpu2 timer i/o control register tior 8 8 2 to 3pclkb 2 iclk 0008 8134h tpu2 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8135h tpu2 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8136h tpu2 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8138h tpu2 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 813ah tpu2 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 8140h tpu3 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8141h tpu3 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8142h tpu3 timer i/o control register h tiorh 8 8 2 to 3pclkb 2 iclk 0008 8143h tpu3 timer i/o control register l tiorl 8 8 2 to 3pclkb 2 iclk 0008 8144h tpu3 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8145h tpu3 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8146h tpu3 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8148h tpu3 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 814ah tpu3 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 814ch tpu3 timer general register c tgrc 16 16 2 to 3pclkb 2 iclk 0008 814eh tpu3 timer general register d tgrd 16 16 2 to 3pclkb 2 iclk 0008 8150h tpu4 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8151h tpu4 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8152h tpu4 timer i/o control register tior 8 8 2 to 3pclkb 2 iclk 0008 8154h tpu4 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8155h tpu4 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8156h tpu4 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8158h tpu4 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 815ah tpu4 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 8160h tpu5 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8161h tpu5 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8162h tpu5 timer i/o control register tior 8 8 2 to 3pclkb 2 iclk 0008 8164h tpu5 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8165h tpu5 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8166h tpu5 timer counter tcnt 16 16 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (14 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 40 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 8168h tpu5 timer general register a tgra 16 16 2 to 3pclkb 2 iclk tpua 0008 816ah tpu5 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 81e6h ppg0 ppg output control register pcr 8 8 2 to 3pclkb 2 iclk ppg 0008 81e7h ppg0 ppg output mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 81e8h ppg0 next data enable registers h nderh 8 8 2 to 3pclkb 2 iclk 0008 81e9h ppg0 next data enable registers l nderl 8 8 2 to 3pclkb 2 iclk 0008 81eah ppg0 output data registers h podrh 8 8 2 to 3pclkb 2 iclk 0008 81ebh ppg0 output data registers l podrl 8 8 2 to 3pclkb 2 iclk 0008 81ech ppg0 next data registers h ndrh 8 8 2 to 3pclkb 2 iclk 0008 81edh ppg0 next data registers l ndrl 8 8 2 to 3pclkb 2 iclk 0008 81eeh ppg0 next data registers h ndrh2 8 8 2 to 3pclkb 2 iclk 0008 81efh ppg0 next data registers l ndrl2 8 8 2 to 3pclkb 2 iclk 0008 8200h tmr0 timer control register tcr 8 8 2 to 3pclkb 2 iclk tmr 0008 8201h tmr1 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8202h tmr0 timer control/status register tcsr 8 8 2 to 3pclkb 2 iclk 0008 8203h tmr1 timer control/status register tcsr 8 8 2 to 3pclkb 2 iclk 0008 8204h tmr0 time constant register a tcora 8 8 2 to 3pclkb 2 iclk 0008 8205h tmr1 time constant register a tcora 8 8* 1 2 to 3pclkb 2 iclk 0008 8206h tmr0 time constant register b tcorb 8 8 2 to 3pclkb 2 iclk 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2 to 3pclkb 2 iclk 0008 8208h tmr0 timer counter tcnt 8 8 2 to 3pclkb 2 iclk 0008 8209h tmr1 timer counter tcnt 8 8* 1 2 to 3pclkb 2 iclk 0008 820ah tmr0 timer counter control register tccr 8 8 2 to 3pclkb 2 iclk 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2 to 3pclkb 2 iclk 0008 820ch tmr0 time count start register tcstr 8 8 2 to 3pclkb 2 iclk 0008 8210h tmr2 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8211h tmr3 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8212h tmr2 timer control/status register tcsr 8 8 2 to 3pclkb 2 iclk 0008 8213h tmr3 timer control/status register tcsr 8 8 2 to 3pclkb 2 iclk 0008 8214h tmr2 time constant register a tcora 8 8 2 to 3pclkb 2 iclk 0008 8215h tmr3 time constant register a tcora 8 8* 1 2 to 3pclkb 2 iclk 0008 8216h tmr2 time constant register b tcorb 8 8 2 to 3pclkb 2 iclk 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2 to 3pclkb 2 iclk 0008 8218h tmr2 timer counter tcnt 8 8 2 to 3pclkb 2 iclk 0008 8219h tmr3 timer counter tcnt 8 8* 1 2 to 3pclkb 2 iclk 0008 821ah tmr2 timer counter control register tccr 8 8 2 to 3pclkb 2 iclk 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2 to 3pclkb 2 iclk 0008 821ch tmr2 time count start register tcstr 8 8 2 to 3pclkb 2 iclk 0008 8280h crc crc control register crccr 8 8 2 to 3pclkb 2 iclk crc 0008 8281h crc crc data input register crcdir 8 8 2 to 3pclkb 2 iclk 0008 8282h crc crc data output register crcdor 16 16 2 to 3pclkb 2 iclk 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2 to 3pclkb 2 iclk riic 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2 to 3pclkb 2 iclk 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2 to 3pclkb 2 iclk 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2 to 3pclkb 2 iclk 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2 to 3pclkb 2 iclk 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2 to 3pclkb 2 iclk 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2 to 3pclkb 2 iclk 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2 to 3pclkb 2 iclk 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2 to 3pclkb 2 iclk 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (15 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 41 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 830ah riic0 slave address register l0 sarl0 8 8 2 to 3pclkb 2 iclk riic 0008 830ah riic0 timeout internal counter l tmocntl 8 8 2 to 3pclkb 2 iclk 0008 830bh riic0 slave address register u0 saru0 8 8 2 to 3pclkb 2 iclk 0008 830bh riic0 timeout internal counter u tmocntu 8 8* 2 2 to 3pclkb 2 iclk 0008 830ch riic0 slave address register l1 sarl1 8 8 2 to 3pclkb 2 iclk 0008 830dh riic0 slave address register u1 saru1 8 8 2 to 3pclkb 2 iclk 0008 830eh riic0 slave address register l2 sarl2 8 8 2 to 3pclkb 2 iclk 0008 830fh riic0 slave address register u2 saru2 8 8 2 to 3pclkb 2 iclk 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2 to 3pclkb 2 iclk 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2 to 3pclkb 2 iclk 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2 to 3pclkb 2 iclk 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2 to 3pclkb 2 iclk 0008 8320h riic1 i 2 c bus control register 1 iccr1 8 8 2 to 3pclkb 2 iclk 0008 8321h riic1 i 2 c bus control register 2 iccr2 8 8 2 to 3pclkb 2 iclk 0008 8322h riic1 i 2 c bus mode register 1 icmr1 8 8 2 to 3pclkb 2 iclk 0008 8323h riic1 i 2 c bus mode register 2 icmr2 8 8 2 to 3pclkb 2 iclk 0008 8324h riic1 i 2 c bus mode register 3 icmr3 8 8 2 to 3pclkb 2 iclk 0008 8325h riic1 i 2 c bus function enable register icfer 8 8 2 to 3pclkb 2 iclk 0008 8326h riic1 i 2 c bus status enable register icser 8 8 2 to 3pclkb 2 iclk 0008 8327h riic1 i 2 c bus interrupt enable register icier 8 8 2 to 3pclkb 2 iclk 0008 8328h riic1 i 2 c bus status register 1 icsr1 8 8 2 to 3pclkb 2 iclk 0008 8329h riic1 i 2 c bus status register 2 icsr2 8 8 2 to 3pclkb 2 iclk 0008 832ah riic1 slave address register l0 sarl0 8 8 2 to 3pclkb 2 iclk 0008 832ah riic1 timeout internal counter l tmocntl 8 8 2 to 3pclkb 2 iclk 0008 832bh riic1 slave address register u0 saru0 8 8 2 to 3pclkb 2 iclk 0008 832bh riic1 timeout internal counter u tmocntu 8 8* 2 2 to 3pclkb 2 iclk 0008 832ch riic1 slave address register l1 sarl1 8 8 2 to 3pclkb 2 iclk 0008 832dh riic1 slave address register u1 saru1 8 8 2 to 3pclkb 2 iclk 0008 832eh riic1 slave address register l2 sarl2 8 8 2 to 3pclkb 2 iclk 0008 832fh riic1 slave address register u2 saru2 8 8 2 to 3pclkb 2 iclk 0008 8330h riic1 i 2 c bus bit rate low-level register icbrl 8 8 2 to 3pclkb 2 iclk 0008 8331h riic1 i 2 c bus bit rate high-level register icbrh 8 8 2 to 3pclkb 2 iclk 0008 8332h riic1 i 2 c bus transmit data register icdrt 8 8 2 to 3pclkb 2 iclk 0008 8333h riic1 i 2 c bus receive data register icdrr 8 8 2 to 3pclkb 2 iclk 0008 8360h riic3 i 2 c bus control register 1 iccr1 8 8 2 to 3pclkb 2 iclk 0008 8361h riic3 i 2 c bus control register 2 iccr2 8 8 2 to 3pclkb 2 iclk 0008 8362h riic3 i 2 c bus mode register 1 icmr1 8 8 2 to 3pclkb 2 iclk 0008 8363h riic3 i 2 c bus mode register 2 icmr2 8 8 2 to 3pclkb 2 iclk 0008 8364h riic3 i 2 c bus mode register 3 icmr3 8 8 2 to 3pclkb 2 iclk 0008 8365h riic3 i 2 c bus function enable register icfer 8 8 2 to 3pclkb 2 iclk 0008 8366h riic3 i 2 c bus status enable register icser 8 8 2 to 3pclkb 2 iclk 0008 8367h riic3 i 2 c bus interrupt enable register icier 8 8 2 to 3pclkb 2 iclk 0008 8368h riic3 i 2 c bus status register 1 icsr1 8 8 2 to 3pclkb 2 iclk 0008 8369h riic3 i 2 c bus status register 2 icsr2 8 8 2 to 3pclkb 2 iclk 0008 836ah riic3 slave address register l0 sarl0 8 8 2 to 3pclkb 2 iclk 0008 836ah riic3 timeout internal counter l tmocntl 8 8 2 to 3pclkb 2 iclk 0008 836bh riic3 slave address register u0 saru0 8 8 2 to 3pclkb 2 iclk 0008 836bh riic3 timeout internal counter u tmocntu 8 8* 2 2 to 3pclkb 2 iclk 0008 836ch riic3 slave address register l1 sarl1 8 8 2 to 3pclkb 2 iclk 0008 836dh riic3 slave address register u1 saru1 8 8 2 to 3pclkb 2 iclk 0008 836eh riic3 slave address register l2 sarl2 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (16 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 42 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 836fh riic3 slave address register u2 saru2 8 8 2 to 3pclkb 2 iclk riic 0008 8370h riic3 i 2 c bus bit rate low-level register icbrl 8 8 2 to 3pclkb 2 iclk 0008 8371h riic3 i 2 c bus bit rate high-level register icbrh 8 8 2 to 3pclkb 2 iclk 0008 8372h riic3 i 2 c bus transmit data register icdrt 8 8 2 to 3pclkb 2 iclk 0008 8373h riic3 i 2 c bus receive data register icdrr 8 8 2 to 3pclkb 2 iclk 0008 8380h rspi0 rspi control register spcr 8 8 2 to 3pclkb 2 iclk rspi 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 to 3pclkb 2 iclk 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 to 3pclkb 2 iclk 0008 8383h rspi0 rspi status register spsr 8 8 2 to 3pclkb 2 iclk 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 to 3pclkb 2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 to 3pclkb 2 iclk 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 to 3pclkb 2 iclk 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 to 3pclkb 2 iclk 0008 838bh rspi0 rspi data control register spdcr 8 8 2 to 3pclkb 2 iclk 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 to 3pclkb 2 iclk 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 to 3pclkb 2 iclk 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 to 3pclkb 2 iclk 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 to 3pclkb 2 iclk 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 to 3pclkb 2 iclk 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 to 3pclkb 2 iclk 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 to 3pclkb 2 iclk 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 to 3pclkb 2 iclk 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 to 3pclkb 2 iclk 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 to 3pclkb 2 iclk 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 to 3pclkb 2 iclk 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 to 3pclkb 2 iclk 0008 83a0h rspi1 rspi control register spcr 8 8 2 to 3pclkb 2 iclk 0008 83a1h rspi1 rspi slave select polarity register sslp 8 8 2 to 3pclkb 2 iclk 0008 83a2h rspi1 rspi pin control register sppcr 8 8 2 to 3pclkb 2 iclk 0008 83a3h rspi1 rspi status register spsr 8 8 2 to 3pclkb 2 iclk 0008 83a4h rspi1 rspi data register spdr 32 16, 32 2 to 3pclkb 2 iclk 0008 83a8h rspi1 rspi sequence control register spscr 8 8 2 to 3pclkb 2 iclk 0008 83a9h rspi1 rspi sequence status register spssr 8 8 2 to 3pclkb 2 iclk 0008 83aah rspi1 rspi bit rate register spbr 8 8 2 to 3pclkb 2 iclk 0008 83abh rspi1 rspi data control register spdcr 8 8 2 to 3pclkb 2 iclk 0008 83ach rspi1 rspi clock delay register spckd 8 8 2 to 3pclkb 2 iclk 0008 83adh rspi1 rspi slave select negation delay register sslnd 8 8 2 to 3pclkb 2 iclk 0008 83aeh rspi1 rspi next-access delay register spnd 8 8 2 to 3pclkb 2 iclk 0008 83afh rspi1 rspi control register 2 spcr2 8 8 2 to 3pclkb 2 iclk 0008 83b0h rspi1 rspi command register 0 spcmd0 16 16 2 to 3pclkb 2 iclk 0008 83b2h rspi1 rspi command register 1 spcmd1 16 16 2 to 3pclkb 2 iclk 0008 83b4h rspi1 rspi command register 2 spcmd2 16 16 2 to 3pclkb 2 iclk 0008 83b6h rspi1 rspi command register 3 spcmd3 16 16 2 to 3pclkb 2 iclk 0008 83b8h rspi1 rspi command register 4 spcmd4 16 16 2 to 3pclkb 2 iclk 0008 83bah rspi1 rspi command register 5 spcmd5 16 16 2 to 3pclkb 2 iclk 0008 83bch rspi1 rspi command register 6 spcmd6 16 16 2 to 3pclkb 2 iclk 0008 83beh rspi1 rspi command register 7 spcmd7 16 16 2 to 3pclkb 2 iclk 0008 8600h mtu3 timer control register tcr 8 8 2 to 3pclkb 2 iclk mtu2a 0008 8601h mtu4 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8602h mtu3 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (17 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 43 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 8603h mtu4 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk mtu2a 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2 to 3pclkb 2 iclk 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2 to 3pclkb 2 iclk 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2 to 3pclkb 2 iclk 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2 to 3pclkb 2 iclk 0008 8608h mtu3 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8609h mtu4 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 860ah mtu timer output master enable register toer 8 8 2 to 3pclkb 2 iclk 0008 860dh mtu timer gate control register tgcr 8 8 2 to 3pclkb 2 iclk 0008 860eh mtu timer output control register 1 tocr1 8 8 2 to 3pclkb 2 iclk 0008 860fh mtu timer output control register 2 tocr2 8 8 2 to 3pclkb 2 iclk 0008 8610h mtu3 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8612h mtu4 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8614h mtu timer cycle data register tcdr 16 16 2 to 3pclkb 2 iclk 0008 8616h mtu timer dead time data register tddr 16 16 2 to 3pclkb 2 iclk 0008 8618h mtu3 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 861ah mtu3 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 861ch mtu4 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 861eh mtu4 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 8620h mtu timer subcounter tcnts 16 16 2 to 3pclkb 2 iclk 0008 8622h mtu timer cycle buffer register tcbr 16 16 2 to 3pclkb 2 iclk 0008 8624h mtu3 timer general register c tgrc 16 16 2 to 3pclkb 2 iclk 0008 8626h mtu3 timer general register d tgrd 16 16 2 to 3pclkb 2 iclk 0008 8628h mtu4 timer general register c tgrc 16 16 2 to 3pclkb 2 iclk 0008 862ah mtu4 timer general register d tgrd 16 16 2 to 3pclkb 2 iclk 0008 862ch mtu3 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 862dh mtu4 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8630h mtu timer interrupt skipping set register titcr 8 8 2 to 3pclkb 2 iclk 0008 8631h mtu timer interrupt skipping counter titcnt 8 8 2 to 3pclkb 2 iclk 0008 8632h mtu timer buffer transfer set register tbter 8 8 2 to 3pclkb 2 iclk 0008 8634h mtu timer dead time enable register tder 8 8 2 to 3pclkb 2 iclk 0008 8636h mtu timer output level buffer register tolbr 8 8 2 to 3pclkb 2 iclk 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2 to 3pclkb 2 iclk 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2 to 3pclkb 2 iclk 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2 to 3pclkb 2 iclk 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2 to 3pclkb 2 iclk 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2 to 3pclkb 2 iclk 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2 to 3pclkb 2 iclk 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2 to 3pclkb 2 iclk 0008 8660h mtu timer waveform control register twcr 8 8, 16 2 to 3pclkb 2 iclk 0008 8680h mtu timer start register tstr 8 8, 16 2 to 3pclkb 2 iclk 0008 8681h mtu timer synchronous register tsyr 8 8, 16 2 to 3pclkb 2 iclk 0008 8684h mtu timer read/write enable register trwer 8 8, 16 2 to 3pclkb 2 iclk 0008 8690h mtu0 noise filter control register nfcr 8 8, 16 2 to 3pclkb 2 iclk 0008 8691h mtu1 noise filter control register nfcr 8 8, 16 2 to 3pclkb 2 iclk 0008 8692h mtu2 noise filter control register nfcr 8 8, 16 2 to 3pclkb 2 iclk 0008 8693h mtu3 noise filter control register nfcr 8 8, 16 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (18 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 44 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 8694h mtu4 noise filter control register nfcr 8 8, 16 2 to 3pclkb 2 iclk mtu2a 0008 8695h mtu5 noise filter control register nfcr 8 8, 16 2 to 3pclkb 2 iclk 0008 8700h mtu0 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8701h mtu0 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2 to 3pclkb 2 iclk 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2 to 3pclkb 2 iclk 0008 8704h mtu0 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8705h mtu0 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8706h mtu0 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8708h mtu0 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 870ah mtu0 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 870ch mtu0 timer general register c tgrc 16 16 2 to 3pclkb 2 iclk 0008 870eh mtu0 timer general register d tgrd 16 16 2 to 3pclkb 2 iclk 0008 8720h mtu0 timer general register e tgre 16 16 2 to 3pclkb 2 iclk 0008 8722h mtu0 timer general register f tgrf 16 16 2 to 3pclkb 2 iclk 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2 to 3pclkb 2 iclk 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2 to 3pclkb 2 iclk 0008 8780h mtu1 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8781h mtu1 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8782h mtu1 timer i/o control register tior 8 8 2 to 3pclkb 2 iclk 0008 8784h mtu1 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8785h mtu1 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8786h mtu1 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8788h mtu1 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 878ah mtu1 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 8790h mtu1 timer input capture control register ticcr 8 8 2 to 3pclkb 2 iclk 0008 8800h mtu2 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 8801h mtu2 timer mode register tmdr 8 8 2 to 3pclkb 2 iclk 0008 8802h mtu2 timer i/o control register tior 8 8 2 to 3pclkb 2 iclk 0008 8804h mtu2 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 8805h mtu2 timer status register tsr 8 8 2 to 3pclkb 2 iclk 0008 8806h mtu2 timer counter tcnt 16 16 2 to 3pclkb 2 iclk 0008 8808h mtu2 timer general register a tgra 16 16 2 to 3pclkb 2 iclk 0008 880ah mtu2 timer general register b tgrb 16 16 2 to 3pclkb 2 iclk 0008 8880h mtu5 timer counter u tcntu 16 16 2 to 3pclkb 2 iclk 0008 8882h mtu5 timer general register u tgru 16 16 2 to 3pclkb 2 iclk 0008 8884h mtu5 timer control register u tcru 8 8 2 to 3pclkb 2 iclk 0008 8886h mtu5 timer i/o control register u tioru 8 8 2 to 3pclkb 2 iclk 0008 8890h mtu5 timer counter v tcntv 16 16 2 to 3pclkb 2 iclk 0008 8892h mtu5 timer general register v tgrv 16 16 2 to 3pclkb 2 iclk 0008 8894h mtu5 timer control register v tcrv 8 8 2 to 3pclkb 2 iclk 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2 to 3pclkb 2 iclk 0008 88a0h mtu5 timer counter w tcntw 16 16 2 to 3pclkb 2 iclk 0008 88a2h mtu5 timer general register w tgrw 16 16 2 to 3pclkb 2 iclk 0008 88a4h mtu5 timer control register w tcrw 8 8 2 to 3pclkb 2 iclk 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2 to 3pclkb 2 iclk 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2 to 3pclkb 2 iclk 0008 88b4h mtu5 timer start register tstr 8 8 2 to 3pclkb 2 iclk 0008 88b6h mtu5 timer compare match clear register tcntcmpclr 8 8 2 to 3pclkb 2 iclk 0008 8900h poe input level control/status register 1 icsr1 16 16 2 to 3pclkb 2 iclk poe2a 0008 8902h poe output level control/status register 1 ocsr1 16 16 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (19 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 45 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 8908h poe input level control/status register 2 icsr2 16 16 2 to 3pclkb 2 iclk poe2a 0008 890ah poe software port output enable register spoer 8 8 2 to 3pclkb 2 iclk 0008 890bh poe port output enable control register 1 poecr1 8 8 2 to 3pclkb 2 iclk 0008 890ch poe port output enable control register 2 poecr2 8 8 2 to 3pclkb 2 iclk 0008 890eh poe input level control/status register 3 icsr3 16 16 2 to 3pclkb 2 iclk 0008 9000h s12ad a/d control register adcsr 16 16 2 to 3pclkb 2 iclk s12adb 0008 9004h s12ad a/d channel select register a adansa 16 16 2 to 3pclkb 2 iclk 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2 to 3pclkb 2 iclk 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2 to 3pclkb 2 iclk 0008 900eh s12ad a/d control extended register adcer 16 16 2 to 3pclkb 2 iclk 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2 to 3pclkb 2 iclk 0008 9012h s12ad a/d conversion extended input control register adexicr 16 16 2 to 3pclkb 2 iclk 0008 9014h s12ad a/d channel select register b adansb 16 16 2 to 3pclkb 2 iclk 0008 9018h s12ad a/d data-doubling register addbldr 16 16 2 to 3pclkb 2 iclk 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2 to 3pclkb 2 iclk 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2 to 3pclkb 2 iclk 0008 9020h s12ad a/d data registers 0 addr0 16 16 2 to 3pclkb 2 iclk 0008 9022h s12ad a/d data registers 1 addr1 16 16 2 to 3pclkb 2 iclk 0008 9024h s12ad a/d data registers 2 addr2 16 16 2 to 3pclkb 2 iclk 0008 9026h s12ad a/d data registers 3 addr3 16 16 2 to 3pclkb 2 iclk 0008 9028h s12ad a/d data registers 4 addr4 16 16 2 to 3pclkb 2 iclk 0008 902ah s12ad a/d data registers 5 addr5 16 16 2 to 3pclkb 2 iclk 0008 902ch s12ad a/d data registers 6 addr6 16 16 2 to 3pclkb 2 iclk 0008 902eh s12ad a/d data registers 7 addr7 16 16 2 to 3pclkb 2 iclk 0008 9030h s12ad a/d data registers 8 addr8 16 16 2 to 3pclkb 2 iclk 0008 9032h s12ad a/d data registers 9 addr9 16 16 2 to 3pclkb 2 iclk 0008 9034h s12ad a/d data registers 10 addr10 16 16 2 to 3pclkb 2 iclk 0008 9036h s12ad a/d data registers 11 addr11 16 16 2 to 3pclkb 2 iclk 0008 9038h s12ad a/d data registers 12 addr12 16 16 2 to 3pclkb 2 iclk 0008 903ah s12ad a/d data registers 13 addr13 16 16 2 to 3pclkb 2 iclk 0008 903ch s12ad a/d data registers 14 addr14 16 16 2 to 3pclkb 2 iclk 0008 903eh s12ad a/d data registers 15 addr15 16 16 2 to 3pclkb 2 iclk 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2 to 3pclkb 2 iclk 0008 9061h s12ad a/d sampling state register l adsstrl 8 8 2 to 3pclkb 2 iclk 0008 9066h s12ad a/d sample and hold circuit control register adshcr 16 16 2 to 3pclkb 2 iclk 0008 9071h s12ad a/d sampling state register o adsstro 8 8 2 to 3pclkb 2 iclk 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2 to 3pclkb 2 iclk 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2 to 3pclkb 2 iclk 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2 to 3pclkb 2 iclk 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2 to 3pclkb 2 iclk 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2 to 3pclkb 2 iclk 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2 to 3pclkb 2 iclk 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2 to 3pclkb 2 iclk 0008 907ah s12ad a/d disconnecting detection control register addiscr 8 8 2 to 3pclkb 2 iclk 0008 a000h sci0 serial mode register smr 8 8 2 to 3pclkb 2 iclk scie, scif 0008 a001h sci0 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a002h sci0 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a003h sci0 transmit data register tdr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (20 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 46 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 a004h sci0 serial status register ssr 8 8 2 to 3pclkb 2 iclk scie, scif 0008 a005h sci0 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a006h sci0 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a007h sci0 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a008h sci0 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a00ch sci0 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a00dh sci0 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a020h sci1 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a021h sci1 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a022h sci1 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a023h sci1 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a024h sci1 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a025h sci1 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a026h sci1 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a027h sci1 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a028h sci1 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a02ch sci1 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a02dh sci1 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a040h sci2 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a041h sci2 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a042h sci2 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a043h sci2 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a044h sci2 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a045h sci2 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a046h sci2 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a047h sci2 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a048h sci2 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a049h sci2 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a04ah sci2 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a04bh sci2 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a04ch sci2 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a04dh sci2 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a060h sci3 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a061h sci3 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a062h sci3 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a063h sci3 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a064h sci3 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a065h sci3 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a066h sci3 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a067h sci3 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a068h sci3 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a069h sci3 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a06ah sci3 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a06bh sci3 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a06ch sci3 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (21 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 47 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 a06dh sci3 spi mode register spmr 8 8 2 to 3pclkb 2 iclk scie, scif 0008 a080h sci4 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a081h sci4 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a082h sci4 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a083h sci4 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a084h sci4 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a085h sci4 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a086h sci4 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a087h sci4 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a088h sci4 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a089h sci4 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a08ah sci4 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a08bh sci4 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a08ch sci4 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a08dh sci4 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a0a0h sci5 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a0a1h sci5 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a0a2h sci5 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a0a3h sci5 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a0a4h sci5 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a0a5h sci5 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a0a6h sci5 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a0a7h sci5 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a0a8h sci5 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a0ach sci5 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a0adh sci5 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a0c0h sci6 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a0c1h sci6 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a0c2h sci6 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a0c3h sci6 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a0c4h sci6 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a0c5h sci6 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a0c6h sci6 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a0c7h sci6 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a0c8h sci6 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a0cch sci6 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a0cdh sci6 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a0e0h sci7 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a0e1h sci7 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a0e2h sci7 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a0e3h sci7 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a0e4h sci7 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a0e5h sci7 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a0e6h sci7 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a0e7h sci7 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (22 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 48 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 a0e8h sci7 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk scie, scif 0008 a0e9h sci7 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a0eah sci7 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a0ebh sci7 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a0ech sci7 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a0edh sci7 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a100h sci8 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a101h sci8 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a102h sci8 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a103h sci8 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a104h sci8 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a105h sci8 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a106h sci8 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a107h sci8 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a108h sci8 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a109h sci8 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a10ah sci8 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a10bh sci8 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a10ch sci8 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a10dh sci8 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a120h sci9 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a121h sci9 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a122h sci9 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a123h sci9 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a124h sci9 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a125h sci9 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a126h sci9 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a127h sci9 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a128h sci9 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a129h sci9 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a12ah sci9 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a12bh sci9 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a12ch sci9 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a12dh sci9 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a140h sci10 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a141h sci10 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a142h sci10 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 a143h sci10 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 a144h sci10 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a145h sci10 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a146h sci10 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a147h sci10 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a148h sci10 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a149h sci10 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a14ah sci10 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a14bh sci10 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a14ch sci10 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a14dh sci10 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 a160h sci11 serial mode register smr 8 8 2 to 3pclkb 2 iclk 0008 a161h sci11 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 a162h sci11 serial control register scr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (23 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 49 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 a163h sci11 transmit data register tdr 8 8 2 to 3pclkb 2 iclk scie, scif 0008 a164h sci11 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 a165h sci11 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 a166h sci11 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 a167h sci11 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 a168h sci11 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 a169h sci11 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 a16ah sci11 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 a16bh sci11 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 a16ch sci11 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 a16dh sci11 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 b000h cac cac control register 0 cacr0 8 8 2 to 3pclkb 2 iclk cac 0008 b001h cac cac control register 1 cacr1 8 8 2 to 3pclkb 2 iclk 0008 b002h cac cac control register 2 cacr2 8 8 2 to 3pclkb 2 iclk 0008 b003h cac cac interrupt request enable register caicr 8 8 2 to 3pclkb 2 iclk 0008 b004h cac cac status register castr 8 8 2 to 3pclkb 2 iclk 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2 to 3pclkb 2 iclk 0008 b008h cac cac lower-limit value setting register callvr 16 16 2 to 3pclkb 2 iclk 0008 b00ah cac cac counter buffer register cacntbr 16 16 2 to 3pclkb 2 iclk 0008 b080h doc doc control register docr 8 8 2 to 3pclkb 2 iclk doc 0008 b082h doc doc data input register dodir 16 16 2 to 3pclkb 2 iclk 0008 b084h doc doc data setting register dodsr 16 16 2 to 3pclkb 2 iclk 0008 b100h elc event link control register elcr 8 8 2 to 3pclkb 2 iclk elc 0008 b102h elc event link setting register 1 elsr1 8 8 2 to 3pclkb 2 iclk 0008 b103h elc event link setting register 2 elsr2 8 8 2 to 3pclkb 2 iclk 0008 b104h elc event link setting register 3 elsr3 8 8 2 to 3pclkb 2 iclk 0008 b105h elc event link setting register 4 elsr4 8 8 2 to 3pclkb 2 iclk 0008 b108h elc event link setting register 7 elsr7 8 8 2 to 3pclkb 2 iclk 0008 b10bh elc event link setting register 10 elsr10 8 8 2 to 3pclkb 2 iclk 0008 b10dh elc event link setting register 12 elsr12 8 8 2 to 3pclkb 2 iclk 0008 b110h elc event link setting register 15 elsr15 8 8 2 to 3pclkb 2 iclk 0008 b111h elc event link setting register 16 elsr16 8 8 2 to 3pclkb 2 iclk 0008 b113h elc event link setting register 18 elsr18 8 8 2 to 3pclkb 2 iclk 0008 b114h elc event link setting register 19 elsr19 8 8 2 to 3pclkb 2 iclk 0008 b115h elc event link setting register 20 elsr20 8 8 2 to 3pclkb 2 iclk 0008 b116h elc event link setting register 21 elsr21 8 8 2 to 3pclkb 2 iclk 0008 b117h elc event link setting register 22 elsr22 8 8 2 to 3pclkb 2 iclk 0008 b118h elc event link setting register 23 elsr23 8 8 2 to 3pclkb 2 iclk 0008 b119h elc event link setting register 24 elsr24 8 8 2 to 3pclkb 2 iclk 0008 b11ah elc event link setting register 25 elsr25 8 8 2 to 3pclkb 2 iclk 0008 b11bh elc event link setting register 26 elsr26 8 8 2 to 3pclkb 2 iclk 0008 b11ch elc event link setting register 27 elsr27 8 8 2 to 3pclkb 2 iclk 0008 b11dh elc event link setting register 28 elsr28 8 8 2 to 3pclkb 2 iclk 0008 b11eh elc event link setting register 29 elsr29 8 8 2 to 3pclkb 2 iclk 0008 b11fh elc event link option setting register a elopa 8 8 2 to 3pclkb 2 iclk 0008 b120h elc event link option setting register b elopb 8 8 2 to 3pclkb 2 iclk 0008 b121h elc event link option setting register c elopc 8 8 2 to 3pclkb 2 iclk 0008 b122h elc event link option setting register d elopd 8 8 2 to 3pclkb 2 iclk 0008 b123h elc port group setting register 1 pgr1 8 8 2 to 3pclkb 2 iclk 0008 b124h elc port group setting register 2 pgr2 8 8 2 to 3pclkb 2 iclk 0008 b125h elc port group control register 1 pgc1 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (24 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 50 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 b126h elc port group control register 2 pgc2 8 8 2 to 3pclkb 2 iclk elc 0008 b127h elc port buffer register 1 pdbf1 8 8 2 to 3pclkb 2 iclk 0008 b128h elc port buffer register 2 pdbf2 8 8 2 to 3pclkb 2 iclk 0008 b129h elc event link port setting register 0 pel0 8 8 2 to 3pclkb 2 iclk 0008 b12ah elc event link port setting register 1 pel1 8 8 2 to 3pclkb 2 iclk 0008 b12bh elc event link port setting register 2 pel2 8 8 2 to 3pclkb 2 iclk 0008 b12ch elc event link port setting register 3 pel3 8 8 2 to 3pclkb 2 iclk 0008 b12dh elc event link software event generation register elsegr 8 8 2 to 3pclkb 2 iclk 0008 b300h sci12 serial mode register smr 8 8 2 to 3pclkb 2 iclk scie, scif 0008 b301h sci12 bit rate register brr 8 8 2 to 3pclkb 2 iclk 0008 b302h sci12 serial control register scr 8 8 2 to 3pclkb 2 iclk 0008 b303h sci12 transmit data register tdr 8 8 2 to 3pclkb 2 iclk 0008 b304h sci12 serial status register ssr 8 8 2 to 3pclkb 2 iclk 0008 b305h sci12 receive data register rdr 8 8 2 to 3pclkb 2 iclk 0008 b306h sci12 smart card mode register scmr 8 8 2 to 3pclkb 2 iclk 0008 b307h sci12 serial extended mode register semr 8 8 2 to 3pclkb 2 iclk 0008 b308h sci12 noise filter setting register snfr 8 8 2 to 3pclkb 2 iclk 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2 to 3pclkb 2 iclk 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2 to 3pclkb 2 iclk 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2 to 3pclkb 2 iclk 0008 b30ch sci12 i 2 c status register sisr 8 8 2 to 3pclkb 2 iclk 0008 b30dh sci12 spi mode register spmr 8 8 2 to 3pclkb 2 iclk 0008 b320h sci12 extended serial module enable register esmer 8 8 2 to 3pclkb 2 iclk 0008 b321h sci12 control register 0 cr0 8 8 2 to 3pclkb 2 iclk 0008 b322h sci12 control register 1 cr1 8 8 2 to 3pclkb 2 iclk 0008 b323h sci12 control register 2 cr2 8 8 2 to 3pclkb 2 iclk 0008 b324h sci12 control register 3 cr3 8 8 2 to 3pclkb 2 iclk 0008 b325h sci12 port control register pcr 8 8 2 to 3pclkb 2 iclk 0008 b326h sci12 interrupt control register icr 8 8 2 to 3pclkb 2 iclk 0008 b327h sci12 status register str 8 8 2 to 3pclkb 2 iclk 0008 b328h sci12 status clear register stcr 8 8 2 to 3pclkb 2 iclk 0008 b329h sci12 control field 0 data register cf0dr 8 8 2 to 3pclkb 2 iclk 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2 to 3pclkb 2 iclk 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2 to 3pclkb 2 iclk 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2 to 3pclkb 2 iclk 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2 to 3pclkb 2 iclk 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2 to 3pclkb 2 iclk 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2 to 3pclkb 2 iclk 0008 b330h sci12 timer control register tcr 8 8 2 to 3pclkb 2 iclk 0008 b331h sci12 timer mode register tmr 8 8 2 to 3pclkb 2 iclk 0008 b332h sci12 timer prescaler register tpre 8 8 2 to 3pclkb 2 iclk 0008 b333h sci12 timer count register tcnt 8 8 2 to 3pclkb 2 iclk 0008 c000h port0 port direction register pdr 8 8 2 to 3pclkb 2 iclk i/o ports 0008 c001h port1 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c002h port2 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c003h port3 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c005h port5 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c006h port6 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c007h port7 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c008h port8 port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c009h port9 port direction register pdr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (25 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 51 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 c00ah porta port direction register pdr 8 8 2 to 3pclkb 2 iclk i/o ports 0008 c00bh portb port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c00ch portc port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c00dh portd port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c00eh porte port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c00fh portf port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c011h porth port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c012h portj port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c013h portk port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c014h portl port direction register pdr 8 8 2 to 3pclkb 2 iclk 0008 c020h port0 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c021h port1 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c022h port2 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c023h port3 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c025h port5 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c026h port6 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c027h port7 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c028h port8 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c029h port9 port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c02ah porta port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c02bh portb port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c02ch portc port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c02dh portd port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c02eh porte port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c02fh portf port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c031h porth port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c032h portj port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c033h portk port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c034h portl port output data register podr 8 8 2 to 3pclkb 2 iclk 0008 c040h port0 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c041h port1 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c042h port2 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c043h port3 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c044h port4 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c045h port5 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c046h port6 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c047h port7 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c048h port8 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c049h port9 port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c04ah porta port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c04bh portb port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c04ch portc port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c04dh portd port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c04eh porte port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c04fh portf port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c051h porth port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c052h portj port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c053h portk port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c054h portl port input data register pidr 8 8 2 to 3pclkb 2 iclk 0008 c060h port0 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c061h port1 port mode register pmr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (26 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 52 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 c062h port2 port mode register pmr 8 8 2 to 3pclkb 2 iclk i/o ports 0008 c063h port3 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c065h port5 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c066h port6 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c067h port7 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c068h port8 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c069h port9 port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c06ah porta port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c06bh portb port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c06ch portc port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c06dh portd port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c06eh porte port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c06fh portf port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c071h porth port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c072h portj port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c073h portk port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c074h portl port mode register pmr 8 8 2 to 3pclkb 2 iclk 0008 c080h port0 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c08ah port5 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c08bh port5 open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c08ch port6 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c08eh port7 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c08fh port7 open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c090h port8 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c092h port9 open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c094h porta open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c095h porta open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c096h portb open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c097h portb open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c098h portc open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c099h portc open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c09dh porte open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c0a6h portk open drain control register 0 odr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c0a7h portk open drain control register 1 odr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c0c0h port0 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c1h port1 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c2h port2 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c3h port3 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c5h port5 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c6h port6 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c7h port7 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c8h port8 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0c9h port9 pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0cah porta pull-up control register pcr 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (27 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 53 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 c0cbh portb pull-up control register pcr 8 8 2 to 3pclkb 2 iclk i/o ports 0008 c0cch portc pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0cdh portd pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0ceh porte pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0cfh portf pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0d1h porth pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0d2h portj pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0d3h portk pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0d4h portl pull-up control register pcr 8 8 2 to 3pclkb 2 iclk 0008 c0e0h port0 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e1h port1 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e2h port2 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e3h port3 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e5h port5 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e6h port6 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e7h port7 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e8h port8 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0e9h port9 drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0eah porta drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0ebh portb drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0ech portc drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0edh portd drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0eeh porte drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0f1h porth drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0f2h portj drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c0f3h portk drive capacity control register dscr 8 8 2 to 3pclkb 2 iclk 0008 c100h mpc cs output enable register pfcse 8 8 2 to 3pclkb 2 iclk mpc 0008 c104h mpc address output enable register 0 pfaoe0 8 8, 16 2 to 3pclkb 2 iclk 0008 c105h mpc address output enable register 1 pfaoe1 8 8, 16 2 to 3pclkb 2 iclk 0008 c106h mpc external bus control register 0 pfbcr0 8 8, 16 2 to 3pclkb 2 iclk 0008 c107h mpc external bus control register 1 pfbcr1 8 8, 16 2 to 3pclkb 2 iclk 0008 c11fh mpc write-protect register pwpr 8 8 2 to 3pclkb 2 iclk 0008 c140h mpc p00 pin function control register p00pfs 8 8 2 to 3pclkb 2 iclk 0008 c141h mpc p01 pin function control register p01pfs 8 8 2 to 3pclkb 2 iclk 0008 c142h mpc p02 pin function control register p02pfs 8 8 2 to 3pclkb 2 iclk 0008 c143h mpc p03 pin function control register p03pfs 8 8 2 to 3pclkb 2 iclk 0008 c145h mpc p05 pin function control register p05pfs 8 8 2 to 3pclkb 2 iclk 0008 c147h mpc p07 pin function control register p07pfs 8 8 2 to 3pclkb 2 iclk 0008 c14ah mpc p12 pin function control registers p12pfs 8 8 2 to 3pclkb 2 iclk 0008 c14bh mpc p13 pin function control registers p13pfs 8 8 2 to 3pclkb 2 iclk 0008 c14ch mpc p14 pin function control registers p14pfs 8 8 2 to 3pclkb 2 iclk 0008 c14dh mpc p15 pin function control registers p15pfs 8 8 2 to 3pclkb 2 iclk 0008 c14eh mpc p16 pin function control registers p16pfs 8 8 2 to 3pclkb 2 iclk 0008 c14fh mpc p17 pin function control registers p17pfs 8 8 2 to 3pclkb 2 iclk 0008 c150h mpc p20 pin function control register p20pfs 8 8 2 to 3pclkb 2 iclk 0008 c151h mpc p21 pin function control register p21pfs 8 8 2 to 3pclkb 2 iclk 0008 c152h mpc p22 pin function control register p22pfs 8 8 2 to 3pclkb 2 iclk 0008 c153h mpc p23 pin function control register p23pfs 8 8 2 to 3pclkb 2 iclk 0008 c154h mpc p24 pin function control register p24pfs 8 8 2 to 3pclkb 2 iclk 0008 c155h mpc p25 pin function control register p25pfs 8 8 2 to 3pclkb 2 iclk 0008 c156h mpc p26 pin function control register p26pfs 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (28 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 54 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 c157h mpc p27 pin function control register p27pfs 8 8 2 to 3pclkb 2 iclk mpc 0008 c158h mpc p30 pin function control registers p30pfs 8 8 2 to 3pclkb 2 iclk 0008 c159h mpc p31 pin function control registers p31pfs 8 8 2 to 3pclkb 2 iclk 0008 c15ah mpc p32 pin function control registers p32pfs 8 8 2 to 3pclkb 2 iclk 0008 c15bh mpc p33 pin function control registers p33pfs 8 8 2 to 3pclkb 2 iclk 0008 c15ch mpc p34 pin function control registers p34pfs 8 8 2 to 3pclkb 2 iclk 0008 c160h mpc p40 pin function control registers p40pfs 8 8 2 to 3pclkb 2 iclk 0008 c161h mpc p41 pin function control registers p41pfs 8 8 2 to 3pclkb 2 iclk 0008 c162h mpc p42 pin function control registers p42pfs 8 8 2 to 3pclkb 2 iclk 0008 c163h mpc p43 pin function control registers p43pfs 8 8 2 to 3pclkb 2 iclk 0008 c164h mpc p44 pin function control registers p44pfs 8 8 2 to 3pclkb 2 iclk 0008 c165h mpc p45 pin function control registers p45pfs 8 8 2 to 3pclkb 2 iclk 0008 c166h mpc p46 pin function control registers p46pfs 8 8 2 to 3pclkb 2 iclk 0008 c167h mpc p47 pin function control registers p47pfs 8 8 2 to 3pclkb 2 iclk 0008 c168h mpc p50 pin function control registers p50pfs 8 8 2 to 3pclkb 2 iclk 0008 c169h mpc p51 pin function control registers p51pfs 8 8 2 to 3pclkb 2 iclk 0008 c16ah mpc p52 pin function control registers p52pfs 8 8 2 to 3pclkb 2 iclk 0008 c16ch mpc p54 pin function control registers p54pfs 8 8 2 to 3pclkb 2 iclk 0008 c16dh mpc p55 pin function control registers p55pfs 8 8 2 to 3pclkb 2 iclk 0008 c16eh mpc p56 pin function control registers p56pfs 8 8 2 to 3pclkb 2 iclk 0008 c170h mpc p60 pin function control registers p60pfs 8 8 2 to 3pclkb 2 iclk 0008 c171h mpc p61 pin function control registers p61pfs 8 8 2 to 3pclkb 2 iclk 0008 c178h mpc p70 pin function control registers p70pfs 8 8 2 to 3pclkb 2 iclk 0008 c17bh mpc p73 pin function control registers p73pfs 8 8 2 to 3pclkb 2 iclk not available in 3-v packages. 0008 c17ch mpc p74 pin function control registers p74pfs 8 8 2 to 3pclkb 2 iclk 0008 c17dh mpc p75 pin function control registers p75pfs 8 8 2 to 3pclkb 2 iclk 0008 c17eh mpc p76 pin function control registers p76pfs 8 8 2 to 3pclkb 2 iclk 0008 c17fh mpc p77 pin function control registers p77pfs 8 8 2 to 3pclkb 2 iclk 0008 c180h mpc p80 pin function control registers p80pfs 8 8 2 to 3pclkb 2 iclk 0008 c181h mpc p81 pin function control registers p81pfs 8 8 2 to 3pclkb 2 iclk 0008 c182h mpc p82 pin function control registers p82pfs 8 8 2 to 3pclkb 2 iclk 0008 c183h mpc p83 pin function control registers p83pfs 8 8 2 to 3pclkb 2 iclk 0008 c186h mpc p86 pin function control registers p86pfs 8 8 2 to 3pclkb 2 iclk 0008 c187h mpc p87 pin function control registers p87pfs 8 8 2 to 3pclkb 2 iclk 0008 c188h mpc p90 pin function control registers p90pfs 8 8 2 to 3pclkb 2 iclk 0008 c189h mpc p91 pin function control registers p91pfs 8 8 2 to 3pclkb 2 iclk 0008 c18ah mpc p92 pin function control registers p92pfs 8 8 2 to 3pclkb 2 iclk 0008 c18bh mpc p93 pin function control registers p93pfs 8 8 2 to 3pclkb 2 iclk 0008 c190h mpc pa0 pin function control registers pa0pfs 8 8 2 to 3pclkb 2 iclk 0008 c191h mpc pa1 pin function control registers pa1pfs 8 8 2 to 3pclkb 2 iclk 0008 c192h mpc pa2 pin function control registers pa2pfs 8 8 2 to 3pclkb 2 iclk 0008 c193h mpc pa3 pin function control registers pa3pfs 8 8 2 to 3pclkb 2 iclk 0008 c194h mpc pa4 pin function control registers pa4pfs 8 8 2 to 3pclkb 2 iclk 0008 c195h mpc pa5 pin function control registers pa5pfs 8 8 2 to 3pclkb 2 iclk 0008 c196h mpc pa6 pin function control registers pa6pfs 8 8 2 to 3pclkb 2 iclk 0008 c197h mpc pa7 pin function control registers pa7pfs 8 8 2 to 3pclkb 2 iclk 0008 c198h mpc pb0 pin function control registers pb0pfs 8 8 2 to 3pclkb 2 iclk 0008 c199h mpc pb1 pin function control registers pb1pfs 8 8 2 to 3pclkb 2 iclk 0008 c19ah mpc pb2 pin function control registers pb2pfs 8 8 2 to 3pclkb 2 iclk 0008 c19bh mpc pb3 pin function control registers pb3pfs 8 8 2 to 3pclkb 2 iclk table 4.1 list of i/o register s (address order) (29 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 55 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 c19ch mpc pb4 pin function control registers pb4pfs 8 8 2 to 3pclkb 2 iclk mpc 0008 c19dh mpc pb5 pin function control registers pb5pfs 8 8 2 to 3pclkb 2 iclk 0008 c19eh mpc pb6 pin function control registers pb6pfs 8 8 2 to 3pclkb 2 iclk 0008 c19fh mpc pb7 pin function control registers pb7pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a0h mpc pc0 pin function control registers pc0pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a1h mpc pc1 pin function control registers pc1pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a2h mpc pc2 pin function control registers pc2pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a3h mpc pc3 pin function control registers pc3pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a4h mpc pc4 pin function control registers pc4pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a5h mpc pc5 pin function control registers pc5pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a6h mpc pc6 pin function control registers pc6pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a7h mpc pc7 pin function control registers pc7pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a8h mpc pd0 pin function control registers pd0pfs 8 8 2 to 3pclkb 2 iclk 0008 c1a9h mpc pd1 pin function control registers pd1pfs 8 8 2 to 3pclkb 2 iclk 0008 c1aah mpc pd2 pin function control registers pd2pfs 8 8 2 to 3pclkb 2 iclk 0008 c1abh mpc pd3 pin function control registers pd3pfs 8 8 2 to 3pclkb 2 iclk 0008 c1ach mpc pd4 pin function control registers pd4pfs 8 8 2 to 3pclkb 2 iclk 0008 c1adh mpc pd5 pin function control registers pd5pfs 8 8 2 to 3pclkb 2 iclk 0008 c1aeh mpc pd6 pin function control registers pd6pfs 8 8 2 to 3pclkb 2 iclk 0008 c1afh mpc pd7 pin function control registers pd7pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b0h mpc pe0 pin function control registers pe0pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b1h mpc pe1 pin function control registers pe1pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b2h mpc pe2 pin function control registers pe2pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b3h mpc pe3 pin function control registers pe3pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b4h mpc pe4 pin function control registers pe4pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b5h mpc pe5 pin function control registers pe5pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b6h mpc pe6 pin function control registers pe6pfs 8 8 2 to 3pclkb 2 iclk 0008 c1b7h mpc pe7 pin function control registers pe7pfs 8 8 2 to 3pclkb 2 iclk 0008 c1bdh mpc pf5 pin function control registers pf5pfs 8 8 2 to 3pclkb 2 iclk 0008 c1c8h mpc ph0 pin function control registers ph0pfs 8 8 2 to 3pclkb 2 iclk 0008 c1c9h mpc ph1 pin function control registers ph1pfs 8 8 2 to 3pclkb 2 iclk 0008 c1cah mpc ph2 pin function control registers ph2pfs 8 8 2 to 3pclkb 2 iclk 0008 c1cbh mpc ph3 pin function control registers ph3pfs 8 8 2 to 3pclkb 2 iclk 0008 c1d1h mpc pj1 pin function control registers pj1pfs 8 8 2 to 3pclkb 2 iclk 0008 c1d3h mpc pj3 pin function control registers pj3pfs 8 8 2 to 3pclkb 2 iclk 0008 c1dah mpc pk2 pin function control registers pk2pfs 8 8 2 to 3pclkb 2 iclk 0008 c1dbh mpc pk3 pin function control registers pk3pfs 8 8 2 to 3pclkb 2 iclk 0008 c1dch mpc pk4 pin function control registers pk4pfs 8 8 2 to 3pclkb 2 iclk 0008 c1ddh mpc pk5 pin function control registers pk5pfs 8 8 2 to 3pclkb 2 iclk 0008 c1e5h mpc pl5 pin function control register pl5pfs 8 8 2 to 3pclkb 2 iclk not available in 5-v packages. 0008 c280h system deep standby control register dpsbycr 8 8 4 to 5pclkb 2 to 3 iclk low power consumption 0008 c282h system deep standby interrupt enable register 0 dpsier0 8 8 4 to 5pclkb 2 to 3 iclk 0008 c284h system deep standby interrupt enable register 2 dpsier2 8 8 4 to 5pclkb 2 to 3 iclk 0008 c286h system deep standby interrupt flag register 0 dpsifr0 8 8 4 to 5pclkb 2 to 3 iclk 0008 c288h system deep standby interrupt flag register 2 dpsifr2 8 8 4 to 5pclkb 2 to 3 iclk 0008 c28ah system deep standby interrupt edge register 0 dpsiegr0 8 8 4 to 5pclkb 2 to 3 iclk 0008 c28ch system deep standby interrupt edge register 2 dpsiegr2 8 8 4 to 5pclkb 2 to 3 iclk 0008 c290h system reset status register 0 rstsr0 8 8 4 to 5pclkb 2 to 3 iclk resets 0008 c291h system reset status register 1 rstsr1 8 8 4 to 5pclkb 2 to 3 iclk table 4.1 list of i/o register s (address order) (30 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 56 of 106 feb 25, 2015 RX634 group 4. i/o registers 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4 to 5pclkb 2 to 3 iclk clock generation circuit 0008 c296h flash flash write erase protection register fwepror 8 8 4 to 5pclkb 2 to 3 iclk flash memory 0008 c297h system voltage monitoring circuit control register lvcmpcr 8 8 4 to 5pclkb 2 to 3 iclk lvda 0008 c298h system voltage detection level select register lvdlvlr 8 8 4 to 5pclkb 2 to 3 iclk 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4 to 5pclkb 2 to 3 iclk 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4 to 5pclkb 2 to 3 iclk 0008 c2a0h to 0008 c2bfh system deep standby backup register 0 to 31 dpsbkr0 to 31 8 8 4 to 5pclkb 2 to 3 iclk low power consumption 000a 0a00h cec cec local address setting register cadr 16 16 1 to 2pclk 1 iclk cec not available in 5-v packages. 000a 0a02h cec cec control register 1 cecctl1 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a04h cec cec transmission start bit width setting register statb 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a06h cec cec transmission start bit low width setting register statl 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a08h cec cec transmission logical 0 low width setting register lgc0l 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a0ah cec cec transmission logical 1 low width setting register lgc1l 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a0ch cec cec transmission data bit width setting register datb 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a0eh cec cec reception data sampling time setting register nomt 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a10h cec cec reception start bit minimum low width setting register statll 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a12h cec cec reception start bit maximum low width setting register statlh 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a14h cec cec reception start bit minimum bit width setting register statbl 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a16h cec cec reception start bit maximum bit width setting register statbh 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a18h cec cec reception logical 0 minimum low width setting register lgc0ll 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a1ah cec cec reception logical 0 maximum low width setting register lgc0lh 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a1ch cec cec reception logical 1 minimum low width setting register lgc1ll 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a1eh cec cec reception logical 1 maximum low width setting register lgc1lh 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a20h cec cec reception data bit minimum bit width setting register datbl 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a22h cec cec reception data bit maximum bit width setting register datbh 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a24h cec cec data bit reference width setting register nomp 16 16 1 to 2pclk 1 iclk not available in 5- v packages. table 4.1 list of i/o register s (address order) (31 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 57 of 106 feb 25, 2015 RX634 group 4. i/o registers 000a 0a28h cec cec extension mode register cecexmd 8 8 1 to 2pclk 1 iclk cec not available in 5-v packages. 000a 0a2ah cec cec extension monitor register cecexmon 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a30h cec cec transmission buffer register ctxd 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a31h cec cec reception buffer register crxd 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a32h cec cec communication error status register ceces 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a33h cec cec communication status register cecs 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a34h cec cec communication error flag clear trigger register cecfc 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0a35h cec cec control register 0 cecctl0 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b00h rcr0 function select register 0 con0 8 8 1 to 2pclk 1 iclk rcr not available in 5-v packages. 000a 0b01h rcr0 function select register 1 con1 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b02h rcr0 status register sts 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b03h rcr0 interrupt control register int 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b04h rcr0 compare control register cpc 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b05h rcr0 compare value setting register cpd 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b06h rcr0 header pattern setting register (min) hdpmin 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b08h rcr0 header pattern setting register (max) hdpmax 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b0ah rcr0 data 0 pattern setting register (min) d0pmin 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b0bh rcr0 data 0 pattern setting register (max) d0pmax 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b0ch rcr0 data 1 pattern setting register (min) d1pmin 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b0dh rcr0 data 1 pattern setting register (max) d1pmax 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b0eh rcr0 special data pattern setting register (min) sdpmin 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b10h rcr0 special data pattern setting register (max) sdpmax 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b12h rcr0 pattern end setting register pe 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b15h rcr0 receive bit count register rbit 8 8 1 to 2pclk 1 iclk not available in 5-v packages. table 4.1 list of i/o register s (address order) (32 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 58 of 106 feb 25, 2015 RX634 group 4. i/o registers 000a 0b16h rcr0 receive data 0 register dat0 8 8 1 to 2pclk 1 iclk rcr not available in 5-v packages. 000a 0b17h rcr0 receive data 1 register dat1 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b18h rcr0 receive data 2 register dat2 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b19h rcr0 receive data 3 register dat3 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b1ah rcr0 receive data 4 register dat4 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b1bh rcr0 receive data 5 register dat5 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b1ch rcr0 receive data 6 register dat6 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b1dh rcr0 receive data 7 register dat7 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b1eh rcr0 measurement result register tim 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b80h rcr1 function select register 0 con0 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b81h rcr1 function select register 1 con1 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b82h rcr1 status register sts 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b83h rcr1 interrupt control register int 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b84h rcr1 compare control register cpc 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b85h rcr1 compare value setting register cpd 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b86h rcr1 header pattern setting register (min) hdpmin 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b88h rcr1 header pattern setting register (max) hdpmax 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b8ah rcr1 data 0 pattern setting register (min) d0pmin 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b8bh rcr1 data 0 pattern setting register (max) d0pmax 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b8ch rcr1 data 1 pattern setting register (min) d1pmin 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b8dh rcr1 data 1 pattern setting register (max) d1pmax 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b8eh rcr1 special data pattern setting register (min) sdpmin 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b90h rcr1 special data pattern setting register (max) sdpmax 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b92h rcr1 pattern end setting register pe 16 16 1 to 2pclk 1 iclk not available in 5-v packages. table 4.1 list of i/o register s (address order) (33 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 59 of 106 feb 25, 2015 RX634 group 4. i/o registers note: this table lists the i/o registers in both 5-v and 3-v package specifications. the i/o registers of each product correspon d to the functions listed in table 1.2. for details, see table 1.2, comparison of functions of different RX634 group products. note: the cec, rcr0, and rcr1 are not available in 5-v packages. note 1. odd addresses cannot be accessed in 16-bit units. when a ccessing a register in 16-bit units, access the address of the t mr0 or tmr2 register. note 2. odd addresses cannot be accessed in 16-bit units. when a ccessing a register in 16-bit units, access the address of the t mocntl register. 000a 0b95h rcr1 receive bit count register rbit 8 8 1 to 2pclk 1 iclk rcr not available in 5-v packages. 000a 0b96h rcr1 receive data 0 register dat0 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b97h rcr1 receive data 1 register dat1 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b98h rcr1 receive data 2 register dat2 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b99h rcr1 receive data 3 register dat3 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b9ah rcr1 receive data 4 register dat4 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b9bh rcr1 receive data 5 register dat5 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b9ch rcr1 receive data 6 register dat6 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b9dh rcr1 receive data 7 register dat7 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0b9eh rcr1 measurement result register tim 16 16 1 to 2pclk 1 iclk not available in 5-v packages. 000a 0c00h system main clock supply control register moscr 8 8 1 to 2pclk 1 iclk clock generation circuit not available in 5-v packages. 000a 0c02h system main clock noise filter control register monfcr 8 8 1 to 2pclk 1 iclk not available in 5-v packages. 007f c402h flash flash mode register fmodr 8 8 2 to 3 fclk 2 to 3 iclk flash memory 007f c410h flash flash access status register fastat 8 8 2 to 3 fclk 2 to 3 iclk 007f c411h flash flash access error interrupt enable register faeint 8 8 2 to 3 fclk 2 to 3 iclk 007f c412h flash flash ready interrupt enable register frdyie 8 8 2 to 3 fclk 2 to 3 iclk 007f c440h flash e2 dataflash read enable register 0 dflre0 16 16 2 to 3 fclk 2 to 3 iclk 007f c442h flash e2 dataflash read enable register 1 dflre1 16 16 2 to 3 fclk 2 to 3 iclk 007f c450h flash e2 dataflash p/e enable register 0 dflwe0 16 16 2 to 3 fclk 2 to 3 iclk 007f c452h flash e2 dataflash p/e enable register 1 dflwe1 16 16 2 to 3 fclk 2 to 3 iclk 007f ffb0h flash flash status register 0 fstatr0 8 8 2 to 3 fclk 2 to 3 iclk 007f ffb1h flash flash status register 1 fstatr1 8 8 2 to 3 fclk 2 to 3 iclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 to 3 fclk 2 to 3 iclk 007f ffb4h flash flash protection register fprotr 16 16 2 to 3 fclk 2 to 3 iclk 007f ffb6h flash flash reset register fresetr 16 16 2 to 3 fclk 2 to 3 iclk 007f ffbah flash fcu command register fcmdr 16 16 2 to 3 fclk 2 to 3 iclk 007f ffc8h flash fcu processing switching register fcpsr 16 16 2 to 3 fclk 2 to 3 iclk 007f ffcah flash e2 dataflash blank check control register dflbccnt 16 16 2 to 3 fclk 2 to 3 iclk 007f ffcch flash flash p/e status register fpestat 16 16 2 to 3 fclk 2 to 3 iclk 007f ffceh flash e2 dataflash blank check status register dflbcstat 16 16 2 to 3 fclk 2 to 3 iclk 007f ffe8h flash peripheral clock notification register pckar 16 16 2 to 3 fclk 2 to 3 iclk table 4.1 list of i/o register s (address order) (34 / 34) address module symbol register name register symbol number of bits access size number of access cycles related function remarks iclk pclk iclk < pclk
r01ds0255ej0100 rev.1.00 page 60 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interferences, insert capacitors of high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, and between the vrefh0 and vrefl0 pins. place capacitors of 0.1 f or so as close to every power pin and use the shortest and heaviest possible traces. note 1. when neither the a/d converter no r the d/a converter is in use, do not leave the avcc0, vrefh/vrefh0, avss0, and vrefl/vrefl0 pins open. connect the avcc0 and vrefh/vrefh0 pins to vcc, and the avss0 and vrefl/vrefl0 pins to vss, respectively. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl = vrefl0 = 0 v item symbol value unit power supply voltage vcc ?0.3 to +6.5 v analog power supply voltage avcc0* 1 ?0.3 to +6.5 v reference power supply voltage vrefh0* 1 ?0.3 to avcc0 + 0.3 v vrefh* 1 ?0.3 to +6.5 v input voltage (except for port 4, ports 03, 05, and 07) v in ?0.3 to vcc + 0.3 v input voltage (port 4, port 07) v in ?0.3 to avcc0 + 0.3 v input voltage (ports 03, 05) v in ?0.3 to vrefh + 0.3 v analog input voltage (ports 4, e) v an ?0.3 to avcc0 + 0.3 v operating temperature t opr ?40 to +85 c storage temperature t stg ?55 to +125 c
r01ds0255ej0100 rev.1.00 page 61 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.2 dc characteristics table 5.2 dc characteristics (1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus) v ih vcc 0.7 ? vcc + 0.3 v port 4, port 07 avcc0 0.8 ? avcc0 + 0.3 ports 03, 05 vrefh 0.8 ? vrefh + 0.3 port l5 vcc 0.8 ? 3.9 conditions 1 except for riic input pin, port 4, ports 03, 05, 07, port l5 vcc 0.8 ? vcc + 0.3 riic input pin (except for smbus) v il ?0.3 ? vcc 0.3 port 4, port 07 ?0.3 ? avcc0 0.2 port 03, 05 ?0.3 ? vrefh 0.2 port l5 ?0.3 ? vcc 0.2 conditions 1 except for riic input pin, port 4, ports 03, 05, 07, port l5 ?0.3 ? vcc 0.2 riic input pin (except for smbus) ?v t vcc 0.05 ? ? port 4, port 07 avcc0 0.06 ? ? ports 03, 05 vrefh 0.06 ? ? port l5 vcc 0.06 ? ? conditions 1 except for riic input pin, port 4, ports 03, 05, 07, port l5 vcc 0.06 ? ? input level voltage (except for schmitt trigger input pins) md, emle v ih vcc 0.9 ? vcc + 0.3 v extal, wait#, tck, rspi input pin vcc 0.8 ? vcc + 0.3 d0 to d15 vcc 0.7 ? vcc + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 conditions 1 cec input pin 2.0 ? 3.9 conditions 1 md, emle v il ?0.3 ? vcc 0.1 extal, wait#, tck, rspi input pin ?0.3 ? vcc 0.2 d0 to d15 ?0.3 ? vcc 0.3 riic input pin (smbus) ?0.3 ? 0.8 conditions 1 cec input pin ?0.3 ? 0.8 conditions 1 cec input pin ?v t ? 0.3 ? conditions 1
r01ds0255ej0100 rev.1.00 page 62 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. supply current values do not include output charge/discharge current from all pins. the values appl y when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. note 3. clocks are supplied to the peripheral functions. this does not include bgo operation. note 4. this is the increase if data is programmed to or er asing from the rom or e2 data flash during program execution. table 5.3 dc characteristics (2) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. test conditions input leakage current res#, md input pin, p35/nmi, extal, port 4 ? i in ? ??1.0 av in = 0 v, vcc three-state leakage current (off-state) ports 12, 13, 16, 17, 20, 21, c0, c1 ? i tsi ? ??5.0 av in = 0 v, vcc except for ports 12, 13, 16, 17, 20, 21, c0, c1 ??1.0 port l5 ? ? 1.8 vcc = 0 v, v in = 3.9 v input capacitance all input pins (except for ports 12, 13, 16, 17, 20, 21, c0, c1) c in ??15pfv in = 0 v, f = 1 mhz, t a = 25 c ports 12, 13, 16, 17, 20, 21, c0, c1 ? ? 30 table 5.4 dc characteristics (3) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol vcc unit test conditions 2.7 to 3.6v 4.0 to 5.5v min. max. min. max. input pull-up mos current all ports (except for ports 03, 05, ports 35 to p37, port 4, port l5) i p ?200 ?10 ?400 ?50 av in = 0 v table 5.5 dc characteristics (4) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 54 mhz i cc 20 ? ma iclk = 54 mhz pclkb = 27 mhz pclkd = 54 mhz fclk = 27 mhz bclk = 54 mhz all peripheral operation: normal* 3 iclk = 54 mhz 24 ? all peripheral operation: max.* 3 iclk = 54 mhz ? 55 sleep mode no peripheral operation iclk = 54 mhz 15.5 ? all peripheral operation: normal iclk = 54 mhz 19.5 ? all-module clock stop mode 14 ? increase during bgo operation* 4 12 ?
r01ds0255ej0100 rev.1.00 page 63 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. supply current values do not include output charge/discharge current from all pins. the values appl y when internal pull- up moss are in the off state. note 2. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is the main c lock. note 3. clocks are supplied to the peripheral functions. this does not include bgo operati on. the clock source is the main clock . note 4. clock supply to the peripheral f unctions is stopped. this does not include bgo operation. the clock source is loco. note 5. clocks are supplied to the peripher al functions. this does not include bgo operation. the clock source is loco. note 6. value when the main clock continues oscillating at 13.5 mhz. note 1. supply current values do not include output charge/discharge current from all pins. the values appl y when internal pull- up moss are in the off state. table 5.6 dc characteristics (5) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol typ. max. unit test conditions supply current* 1 low-speed operating mode 1 normal operating mode no peripheral operation* 2 iclk = 1 mhz i cc 4?ma all peripheral operation: normal* 3 iclk = 1 mhz 4.2 ? all peripheral operation: max.* 3 iclk = 1 mhz ? 15 sleep mode no peripheral operation iclk = 1 mhz 3.8 ? all peripheral operation: normal iclk = 1 mhz 4.0 ? all-module clock stop mode 3.7 ? low-speed operating mode 2 normal operating mode no peripheral operation* 4 iclk = 125 khz 0.4 ? all peripheral operation: normal* 5 iclk = 125 khz 0.5 ? all peripheral operation: max.* 5 iclk = 125 khz ? 8* 6 sleep mode no peripheral operation iclk = 125 khz 0.3 ? all peripheral operation: normal iclk = 125 khz 0.4 ? all-module clock stop mode 0.28 ? table 5.7 dc characteristics (6) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol typ. max. unit test conditions supply power* 1 software standby mode i cc 40 1000 a deep software standby mode ram power supplied 22 200 ram power not supplied power-on reset circuit low power consumption function disabled 21 60 power-on reset circuit low power consumption function enabled 6.2 28
r01ds0255ej0100 rev.1.00 page 64 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. total power dissipated by the entire chip (including output currents) note: the values for a/d conv ersion apply when the sample and hold circuit is not in use. note 1. the reference power supply current is included in the power supply current value for d/a conversion. note 2. the value is the total value of i avcc0 and i vrefh . table 5.8 dc characteristics (7) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol typ. max. unit test conditions permissible total consumption power* 1 pd ? 360 mw table 5.9 dc characteristics (8) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions analog power supply current during a/d conversion i avcc0 ? 1.9 4.2 ma conditions 1 ? 2.5 4.2 ma conditions 2 waiting for a/d conversion ? 0.1 4 a during d/a conversion (per channel) i vrefh * 1 ? 0.3 1 ma conditions 1 ? 0.46 1 ma conditions 2 waiting for a/d, d/a conversion (all units)* 2 ? ? 23 40 a reference power supply current during a/d conversion i vrefh0 ? 0.44 1.5 ma conditions 1 ? 0.66 1.5 ma conditions 2 waiting for a/d conversion ? 0.1 1 a table 5.10 dc characteristics (9) conditions: vcc = avcc0 = 0 to 5.5 v, vref h = 0 to avcc0, vrefh0 = 0 to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions vcc rising gradient srvcc ? ? 20 ms/v at cold start table 5.11 permissible output currents conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol max. unit permissible output low current (average value per 1 pin) normal output mode i ol 2.0 ma permissible output low current (maximum value per 1 pin) normal output mode 4.0 ma permissible output low current (total) total of all output pins ? i ol 80 ma permissible output high current (average value per 1 pin) normal output mode i oh ?2.0 ma permissible output high current (maximum value per 1 pin) normal output mode ?4.0 ma permissible output high current (total) total of all output pins ? i oh ?80 ma
r01ds0255ej0100 rev.1.00 page 65 of 106 feb 25, 2015 RX634 group 5. electrical characteristics table 5.12 output valu es of voltage (1) conditions: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output v ol ?0.5vi ol = 1.0 ma high-drive output ? 0.5 i ol = 2.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma cec pins ? 0.6 i ol = 2.1 ma output high all output pins normal output v oh vcc ? 0.5 ? v i oh = ?1.0 ma high-drive output vcc ? 0.5 ? i oh = ?2.0 ma table 5.13 output valu es of voltage (2) conditions: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output v ol ?0.8vi ol = 2.0 ma high-drive output ? 0.8 i ol = 4.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma output high all output pins normal output v oh vcc ? 0.8 ? v i oh = ?2.0 ma high-drive output vcc ? 0.8 ? i oh = ?4.0 ma
r01ds0255ej0100 rev.1.00 page 66 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3 ac characteristics note 1. the lower-limit frequency of fclk is 4 mhz during programming or erasing of the flash memory. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. note 1. programming and erasing t he flash memory is impossible. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. note 1. programming and erasing t he flash memory is impossible. note 2. the a/d converter cannot be used. table 5.14 operation frequency value (high-speed operating mode) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit operating frequency system clock (iclk) f max ??5 4m h z flashif clock (fclk)* 1 ??3 2 peripheral module clock (pclkb) ? ? 32 peripheral module clock (pclkd)* 2 ??5 4 external bus clock (bclk) ? ? 54 bclk pin output ? ? 27 table 5.15 operation frequency value (low-speed operating mode 1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vref h = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vref h = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit operating frequency system clock (iclk) f max ?? 1m h z flashif clock (fclk)* 1 ?? 1 peripheral module clock (pclkb) ? ? 1 peripheral module clock (pclkd)* 2 ?? 1 external bus clock (bclk) ? ? 1 bclk pin output ? ? 1 table 5.16 operation frequency value (low-speed operating mode 2) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit operating frequency system clock (iclk) f max ? ? 143.75 khz flashif clock (fclk)* 1 ? ? 143.75 peripheral module clock (pclkb) ? ? 143.75 peripheral module clock (pclkd)* 2 ? ? 143.75 external bus clock (bclk) ? ? 143.75 bclk pin output ? ? 143.75
r01ds0255ej0100 rev.1.00 page 67 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3.1 clock timing note 1. when the extal external clock input is used with divided by 1 to output from t he bclk pin, the above should be satisfied with a duty cycle of 45 to 55%. table 5.17 bclk timing conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 37 ? ? ns figure 5.1 bclk pin output high pulse width* 1 t ch 5??ns bclk pin output low pulse width* 1 t cl 5??ns bclk pin output rising time t cr ?? 5 ns bclk pin output falling time t cf ?? 5 ns table 5.18 clock timing conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions extal external clock input cycle time t excyc 50 (62.5)* 1 ? ? ns figure 5.2 extal external clock input high pulse width t exh 20 (25)* 1 ??ns extal external clock input low pulse width t exl 20 (25)* 1 ??ns extal external clock rising time t exr ?? 5 ns extal external clock falling time t exf ?? 5 ns extal external clock input wait time* 2 t exwt 1? ? ms main clock oscillator oscillation frequency* 3 f main 8? 20 (16)* 1 mhz main clock oscillation stabilization time (crystal) f mainosc ?? * 3 ms figure 5.3 main clock oscillation stabilization wait time (crystal) f mainoscwt ?? * 4 ms loco clock cycle time t lococyc 6.96 8 9.4 s loco clock cycle time t lococyc 7.27 8 8.89 st a = 0 to +60c loco clock oscillation frequency f loco 106.25 125 143.75 khz loco clock oscillation frequency f loco 112.5 125 137.5 khz t a = 0 to +60c loco clock oscillation stabilization wait time t locowt ?? 20 s figure 5.4 pll input frequency f pllin 4? 20 mhz pll circuit oscillation frequency t locowt 104 ? 200 mhz pll clock oscillation stabilization time pll operation started after main clock oscillation has settled t pll1 ? ? 500 s figure 5.5 pll clock oscillation stabilization wait time t pllwt1 ?? * 5 ms pll clock oscillation stabilization time pll operation started before main clock oscillation has settled t pll2 ??t mainosc + t pll1 ms figure 5.6 pll clock oscillation stabilization wait time t pllwt2 ?? * 5 ms
r01ds0255ej0100 rev.1.00 page 68 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. the values in parentheses indicate when the monfcr regi ster is set to a value other than a5h (noise filter enabled) whil e cecmclk is selected as the cec operating clock and rcrmclk is selected as the rcr operating clock. note 2. time until the clock can be used after the main clock oscillator stop bit (mosccr.most p) is set to 0 (operating). note 3. when using a main clock, request the oscillator manufacturer to evaluate the oscillator. for the oscillation stabilizati on time, refer to the evaluation results obtained from the oscillator manufacturer. note 4. the number of cycles n selected by the value of the mo scwtcr.msts[4:0] bits determines the main-clock oscillation stabilization waiting time in accord with the formula below. note 5. the number of cycles n selected by the value of the pllw tcr.psts[4:0] bits determines t he pll-clock oscillation stabiliz ation waiting time in accord with the formula below. figure 5.1 bclk pin output timing figure 5.2 extal external clock input timing figure 5.3 main clock oscillation start timing t mainoscwt = t mainosc + n +16384 f main t pllwt1 = t pll1 + n +131072 f pll t pllwt2 = t pll2 + = t mainosc + t pll1 + n +131072 f pll n +131072 f pll t cf t ch t bcyc t cr t cl bclk pin output test conditions: v oh = vcc 0.7, v ol = vcc 0.3, i oh = ? 1.0 ma, i ol = 1.0 ma, c = 30 pf t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillator output mosccr.mostp t mainosc main clock t mainoscwt
r01ds0255ej0100 rev.1.00 page 69 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.4 loco clock oscillation start timing figure 5.5 pll clock oscillation start timing (pll is operated after main clock oscillation has settled) figure 5.6 pll clock oscillation st art timing (pll is operated befo re main clock oscillation has settled) loco clock lococr.lcstp t locowt pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output pll circuit output t pll1 t pllwt1 mosccr.mostp pll circuit output pllcr2.pllen t pll2 t mainosc main clock oscillator output pll clock t pllwt2
r01ds0255ej0100 rev.1.00 page 70 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3.2 reset timing figure 5.7 reset input timing at power-on figure 5.8 reset input timing table 5.19 reset timing conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions res# pulse width power-on t reswp 2 ? ? ms figure 5.7 deep software standby mode t reswd 1 ? ? ms figure 5.8 software standby mode, low-speed operating modes 1 and 2 t resws 1??ms programming or erasure of the rom or e2 dataflash memory or blank checking of the e2 dataflash memory t reswf 200 ? ? s other than above t resw 200 ? ? s wait time after res# cancellation t reswt 59 ? 60 t cyc figure 5.7 internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) t resw2 112 ? 120 t cyc vcc res# t reswp internal reset t reswt res# internal reset t reswt t reswd, t resws, t reswf, t resw
r01ds0255ej0100 rev.1.00 page 71 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note: the wait time varies depending on the state in which each oscillator was when the wait instruction was executed. the recov ery time when multiple oscillators are operating is the same period as that when the osci llator which requires the longest time of all operating oscillators to recover is operating alone. figure 5.9 software standby mode cancellation timing table 5.20 timing of recovery from low power consumption modes conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode crystal resonator connected to main clock oscillator main clock oscillator operating t sbymc 10 ? ? ms figure 5.9 main clock oscillator and pll circuit operating t sbypc 10 ? ? ms external clock input to main clock oscillator main clock oscillator operating t sbyex 1??ms main clock oscillator and pll circuit operating t sbype 1??ms low-speed on-chip oscillator or iwdt-dedicated on-chip oscillator operating t sbylo ? ? 800 s recovery time after cancellation of deep software standby mode t dsby ? ? 1 ms figure 5.10 wait time after cancellation of deep software standby mode t dsbywt 45 ? 46 t cyc oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo
r01ds0255ej0100 rev.1.00 page 72 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.10 deep software standby mode cancellation timing oscillator irq internal reset exceptional reset handling starts deep software standby mode deep software standby reset t dsby t dsbywt
r01ds0255ej0100 rev.1.00 page 73 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3.4 control signal timing note: 200 ns minimum in deep software standby and software standby modes. figure 5.11 nmi interrupt input timing figure 5.12 irq interrupt input timing table 5.21 control signal timing conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns t c (pclkb) 2 200ns, figure 5.11 t c (pclkb) 2 ? ? ns t c (pclkb) 2 > 200ns, figure 5.11 irq pulse width t irqw 200 ? ? ns t c (pclkb) 2 200ns, figure 5.12 t c (pclkb) 2 ? ? ns t c (pclkb) 2 > 200ns, figure 5.12 nmi t nmiw irq t irqw
r01ds0255ej0100 rev.1.00 page 74 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3.5 bus timing table 5.22 bus timing (1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c fbclk 54 mhz (bclk pin output frequency 27 mhz), voh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, cl = 30 pf item symbol min. max. unit test conditions address delay time t ad ? 30 ns figure 5.13 to figure 5.16 byte control delay time t bcd ?3 0n s cs# delay time t csd ?3 0n s rd# delay time t rsd ?3 0n s read data setup time t rds 20 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?3 0n s write data delay time t wdd ?3 0n s write data hold time t wdh 0?n s wait# setup time t wts 20 ? ns figure 5.17 wait# hold time t wth 0?n s
r01ds0255ej0100 rev.1.00 page 75 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.13 external bus timing/normal read cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) bus write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t w1 t w2 t end t n1 t n2 rdon:1 csrwait:2 csroff:2 cson:0 t bcd t csd
r01ds0255ej0100 rev.1.00 page 76 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.14 external bus timing/normal write cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t ad t ad t ad d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t n2 wron:1 wdon:1 *1 cswwait:2 wdoff:1 *1 cson:0 note 1. set the values of wdon and wdoff to 1 or greater. t bcd t csd cswoff:2
r01ds0255ej0100 rev.1.00 page 77 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.15 external bus timing/page read cycle (bus clock synchronized) figure 5.16 external bus timing/page write cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd rd# (read) t rsd t rsd t rdh t rds t ad t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t end t pw1 t pw2 t end t n1 t n2 t ad t ad t ad t ad rdon:1 csrwait:2 csroff:2 t rsd t rsd t rdh t rds t ad t ad csprwait:2 t pw1 t pw2 t end rdon:1 csprwait:2 rdon:1 csprwait:2 rdon:1 cson:0 t bcd t csd a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t ad t w1 d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t n2 t dw1 t ad t ad t ad t ad wron:1 wdon:1 *1 cswwait:2 cspwwait:2 wdoff:1 *1 cspwwait:2 wdoff:1 *1 wdoff:1 *1 cson:0 wron:1 wdon:1 *1 wron:1 wdon:1 *1 note 1. set the values of wdon and wdoff to 1 or greater. t bcd t csd cswoff:2
r01ds0255ej0100 rev.1.00 page 78 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.17 external bus timing/external wait control table 5.23 bus timing (multiplexed bus) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c fbclk 54 mhz (bclk pin output frequency 27 mhz), voh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, cl = 30 pf item symbol min. max. unit test conditions address delay time t ad ? 30 ns figure 5.18, figure 5.19 byte control delay time t bcd ?3 0n s cs# delay time t csd ?3 0n s rd# delay time t rsd ?3 0n s ale delay time t aled ?3 0n s read data setup time t rds 20 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?3 0n s write data delay time t wdd ?3 0n s write data hold time t wdh 0?n s wait# setup time t wts 20 ? ns figure 5.17 wait# hold time t wth 0?n s t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a23 to a0 cs3# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t h external wait
r01ds0255ej0100 rev.1.00 page 79 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.18 example of operation in read access over the external bus (multiplexed) figure 5.19 example of operation in write access over the external bus (multiplexed) address/ data bus data read (rd#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t wn t ad t ad t su(db-rd) 40 ns (min) t end address cycle data cycle t aled t csd t csd t n1 t h 1 cycle fixed address cycle wait (await) t s(db-rd) 0 ns (min) t rsd t rss t rsd t rss read-access cs extension cycle (csroff) t aled rd assert wait (rdon) normal read cycle wait (csrwait) cs assert wait (cson) a d t rdh t rds t d(ad-ale) t h(ale-ad) address/ data bus data write (wr#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t ad t ad t end address cycle data cycle t csd t csd t n1 t h 1 cycle fixed t d(bclk-ale)= t aled address cycle wait (await) t rsd t rss t rsd t rss wr assert wait (wron) normal write cycle wait (csrwait) a d write data output wait (wdon) t d(bclk-ale)= t aled a read-access cs extension cycle (csroff)
r01ds0255ej0100 rev.1.00 page 80 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.3.6 timing of on-chi p peripheral modules note 1. t pcyc : pclkb cycle note 2. t cac : cac count clock source cycle table 5.24 timing of on-chi p peripheral modules (1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c when high-drive output is selected by the drive capacity control register conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c when high-drive output is selected by the drive capacity control register item symbol min. max. unit *1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.20 mtu/tpu input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.21 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.22 both-edge setting 2.5 ? phase counting mode 2.5 ? poe poe# input pulse width t poew 1.5 ? t pcyc figure 5.23 tmr timer clock pulse width single-edge setting t tmcwh, t tmcwl 1.5 ? t pcyc figure 5.24 both-edge setting 2.5 ? sci input clock cycle asynchronous t scyc 4?t pcyc figure 5.25 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?2 0n s input clock fall time t sckf ?2 0n s output clock cycle asynchronous t scyc 16 ? t pcyc figure 5.26 clock synchronous 4 ? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?2 0n s output clock fall time t sckf ?2 0n s transmit data delay time clock synchronous t txd ?4 0n s receive data setup time clock synchronous t rxs 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.27 cac cacref input pulse width t pcyc t cac *2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac *2 5 t cac + 6.5 t pcyc ?ns
r01ds0255ej0100 rev.1.00 page 81 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. t pcyc : pclkb cycle table 5.25 timing of on-chi p peripheral modules (2) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c when high-drive output is selected by the drive capacity control register conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c when high-drive output is selected by the drive capacity control register item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc figure 5.28 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/ fall time output t spckr, t spckf ?5n s input ? 1 s data input setup time master t su 15 ? ns figure 5.29 to figure 5.34 slave 20 ? t pcyc ? data input hold time master pclkb set to a division ratio other than divided by 2 t h t pcyc ?n s pclkb set to divided by 2 0? slave 20 + 2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master t od ?1 8n s slave ? 3 t pcyc + 40 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/ fall time output t dr, t df ?5n s input ? 1 s ssl rise/fall time output t sslr, t sslf ?5n s input ? 1 s slave access time t sa ?4t pcyc figure 5.33, figure 5.34 slave output release time t rel ?3t pcyc
r01ds0255ej0100 rev.1.00 page 82 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. t pcyc : pclkb cycle table 5.26 timing of on-chi p peripheral modules (3) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c when high-drive output is selected by the drive capacity control register conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c when high-drive output is selected by the drive capacity control register item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 5.28 sck clock cycle input (slave) 8 65536 sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time t su 40 ? ns figure 5.29 to figure 5.34 data input hold time t h 40 ? ns ss input setup time t lead 6?t pcyc ss input hold time t lag 6?t pcyc data output delay time t od ?40ns data output hold time t oh ?10 ? ns data rise/fall time t dr , t df ?20ns ss input rise/fall time t sslr , t sslf ?20ns slave access time t sa ?5t pcyc figure 5.33, figure 5.34 slave output release time t rel ?5t pcyc
r01ds0255ej0100 rev.1.00 page 83 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note: t iiccyc : riic internal reference count clock (iic ) cycle note 1. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the i cfer.nfe bits = 1. note 2. c b indicates the total capacity of the bus line. table 5.27 timing of on-chi p peripheral modules (4) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. ( * 1, * 2) max. unit test conditions riic (standard-mode) scl input cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.35 scl input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda input rise time t sr ? 1000 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast-mode) scl input cycle time t scl 6 (12) t iiccyc + 600 ? ns scl input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0255ej0100 rev.1.00 page 84 of 106 feb 25, 2015 RX634 group 5. electrical characteristics note 1. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the i cfer.nfe bits = 1. note 2. c b indicates the total capacity of the bus line. note 3. t pcyc : pclkb cycle note 1. cb: communication line load capacitance; rb: communication line external pull-up resistance figure 5.20 i/o port input timing table 5.28 timing of on-chi p peripheral modules (5) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. ( * 1, * 2) max.* 3 unit test conditions simple iic (standard-mode) scl, sda input rise time t sr ? 1000 ns figure 5.35 scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 04 t pcyc ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple iic (fast-mode) scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 04 t pcyc ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf table 5.29 timing of on-chi p peripheral modules (6) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. max. unit test conditions cec fall time t cf ?5 0 sc b = 1600 pf, r b = 27 k ? c b = 7700 pf, r b = 3 k ? port pclkb t prw
r01ds0255ej0100 rev.1.00 page 85 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.21 mtu/tpu input/output timing figure 5.22 mtu/tpu clock input timing figure 5.23 poe# input timing figure 5.24 8-bit timer clock input timing output compare output input capture input pclkb t ticw mtclka (tclka) to mtclkd (tclkd) pclkb t tckwl t tckwh poen# input pclkb t poew pclkb tmci0 to tmci3 t tmcwl t tmcwh
r01ds0255ej0100 rev.1.00 page 86 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.25 sck clock input timing figure 5.26 sci input/output timing: clock synchronous mode figure 5.27 a/d converter external trigger input timing t sckw t sckr t sckf t scyc sckn (n = 0 to 12) t txd t rxs t rxh txdn rxdn sckn n = 0 to 12 adtrg0# pclkb t trgw
r01ds0255ej0100 rev.1.00 page 87 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.28 rspi clock timing and simple spi clock timing figure 5.29 rspi timing (master, cpha = 0) (bit rate: pclkb set to division ratio other than divided by 2) and simple spi timing (master, ckph = 1) simple spi sckn master select output sckn slave select input (n = 0 to 12) t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc rspcka slave select input rspi rspcka master select output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to 3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output (n = 0 to 12)
r01ds0255ej0100 rev.1.00 page 88 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.30 rspi timing (master, cpha = 0) (bit rate: pclkb set to divided by 2) figure 5.31 rspi timing (master, cpha = 1) (bit rate: pclkb set to division ratio other than divided by 2) and simple spi timing (master, ckph = 0) lsb in t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in msb out data lsb out idle msb out ssla0 to 3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output msb in data t hf ssla0 to 3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output (n = 0 to 12) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od
r01ds0255ej0100 rev.1.00 page 89 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.32 rspi timing (master, cpha = 1) (bit rate: pclkb set to divided by 2) figure 5.33 rspi timing (s lave, cpha = 0) and simple spi timing (slave, ckph = 1) t dr, t df t hf t lead t td t lag t sslr, t sslf t oh data msb in msb out data lsb out idle msb out t od ssla0 to 3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output msb in lsb in t su t h t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input rspi simple spi sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input (n = 0 to 12) ssn# input
r01ds0255ej0100 rev.1.00 page 90 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.34 rspi timing (s lave, cpha = 1) and simple spi timing (slave, ckph = 0) figure 5.35 riic bus interface input/output timing and simple iic bus interface input/output timing t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out smosin input (n = 0 to 12) ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input rspi simple spi sckn ckpol = 1 input sckn ckpol = 0 input smison output ssn# input sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf note 1. s, p, and sr indicate the following conditions, respectively. s: start condition p: stop condition sr: restart condition test conditions v ih = vcc 0.7, v il = vcc 0.3 sr *1
r01ds0255ej0100 rev.1.00 page 91 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.4 a/d conversion characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note: when using the channel-dedicated sample-and-hold ci rcuit, use the an000 to an002 analog input voltage (v an ) that satisfies all the following conditions: 0.25 v v an avcc0 - 0.25 v, v an vrefh0, and avcc0 2.7 v. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. table 5.30 a/d conversion characteristics conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item min. typ. max. unit test conditions a/d conversion clock frequency (fpclkd) 1 ? 54 mhz resolution ? ? 12 bit conversion time* 1 (ad clock = 54 mhz) permissible signal source impedance = 1.0 k ? 1 (0.4)* 2 ?? s high-precision channel permissible signal source impedance = 1 k ? , avcc 4.0 v 1.9 (1.3)* 2 ? ? normal-precision channel permissible signal source impedance = 1 k ? , avcc 2.7 v 2.5 (1.9)* 2 ?? analog input capacitance ? ? 30 pf offset error ? 2.0 6.0 lsb high-precision channel (sh used) ? 1.5 3.0 high-precision channel (sh not used) ? 2.0 7.5 normal-precision channel full-scale error ? 2.0 6.0 lsb high-precision channel (sh used) ? 1.5 3.0 high-precision channel (sh not used) ? 2.0 7.5 normal-precision channel quantization error ? 0.5 ? lsb absolute accuracy ? 4.0 8.0 lsb high-precision channel (sh used) ? 2.0 6.0 high-precision channel (sh not used) ? 2.5 8.0 normal-precision channel dnl differential nonlinearity error ? 2.0 6.0 lsb high-precision channel (sh used) ? 1.5 3.0 high-precision channel (sh not used) ? 2.0 4.0 normal-precision channel inl integral nonlinearity error ? 2.0 6 .0 lsb high-precision channel (sh used) ? 1.5 3.0 high-precision channel (sh not used) ? 2.0 4.0 normal-precision channel table 5.31 sampling time conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol typ. unit test conditions sampling time high-precision channel ts 0.2 + 0.16 r0 (k ? ) s figure 5.36 normal-precision channel 0.3 + 0.16 r0 (k ? )
r01ds0255ej0100 rev.1.00 page 92 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.36 internal equivalent circuit of analog input pin table 5.32 a/d converter channel classification classification target channel channel-dedicated sample-and-hold circuit condition high-accuracy channels an000 to an002 used avcc0 = vrefh0 = 2.7 to 3.6v (3-v package) avcc0 = vrefh0 = 4.0 to 5.5v (5-v package) avss0 = vrefl0 = 0v 0.25v v an avcc0 ? 0.25v v an vrefh0 not used avcc0 = vrefh0 = 2.7 to 3.6v (3-v package) avcc0 = vrefh0 = 4.0 to 5.5v (5-v package) avss0 = vrefl0 = 0v 0v v an vrefh0 an003 to an007 ? normal-accuracy channels an008 to an015 ? r0 ani RX634
r01ds0255ej0100 rev.1.00 page 93 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.37 illustration of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0 = 5.12 v), then 1-lsb width becomes 1.25 mv, and 0 mv, 1.25 mv, 2.5 mv , ... are used as analog input voltages. if analog input voltage is 10 mv, absolu te accuracy = 5 lsb means that the actua l a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expect ed from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0255ej0100 rev.1.00 page 94 of 106 feb 25, 2015 RX634 group 5. electrical characteristics differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actually output code. offset error offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point of the ideal last output code and the actual last output code.
r01ds0255ej0100 rev.1.00 page 95 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.5 d/a conversion characteristics table 5.33 d/a conversion characteristics (1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item min. typ. max. unit test conditions resolution ? ? 10 bit conversion time ? ? 3.0 s 20-pf capacitive load absolute accuracy ? 3.0 5.0 lsb 4-m ? resistive load ?? 4 . 0l s b8 - m ? resistive load ro output resistance ? 3.6 ? k ?
r01ds0255ej0100 rev.1.00 page 96 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.6 power-on reset circuit and voltage detecti on circuit characteristics note 1. # in the symbol v det1_# denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note 2. # in the symbol v det2 _# denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. note 3. the minimum vcc down time indicates the time when v cc is below the minimum value of voltage detection levels v por , v det1 , and v det2 for the por/lvd. note 1. # in the symbol v det1_# denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note 2. # in the symbol v det2 _# denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. note 3. the minimum vcc down time indicates the time when v cc is below the minimum value of voltage detection levels v por , v det1 , and v det2 for the por/lvd. table 5.34 power-on reset circuit and voltage detection circuit characteristics (1) conditions: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 2.46 2.58 2.7 v figure 5.38 voltage detection circuit (lvd0) v det0 2.7 2.82 2.94 figure 5.39 voltage detection circuit (lvd1)* 1 v det1_8 2.75 2.90 3.05 figure 5.40 v det1_9 2.70 2.85 3.00 v det1_a 2.73 2.88 3.03 voltage detection circuit (lvd2)* 2 v det2_8 2.75 2.90 3.05 figure 5.41 v det2_9 2.70 2.85 3.00 v det2_a 2.73 2.88 3.03 internal reset time power-on reset (por) t por 9.7 ms figure 5.38 voltage detection circuit (lvd0) t lvo0 9.7 figure 5.39 voltage detection circuit (lvd1) t lvo1 0.9 figure 5.40 voltage detection circuit (lvd2) t lvo2 0.9 figure 5.41 minimum vcc down time* 3 t voff 200 ? ? s figure 5.39 to figure 5.41 response delay time t det 200 s lvd operation stabilization time (after lvd is enabled) td (e-a) 3 s figure 5.40, figure 5.41 hysteresis width (lvd1 and lvd2) v lvh 80 mv table 5.35 power-on reset circuit and voltage detection circuit characteristics (2) conditions: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 3.6 3.8 4.0 v figure 5.38 voltage detection circuit (lvd0) v det0 4.0 4.2 4.4 figure 5.39 voltage detection circuit (lvd1)* 1 v det1_8 4.59 4.77 4.95 figure 5.40 v det1_9 4.05 4.23 4.41 v det1_a 4.32 4.50 4.68 voltage detection circuit (lvd2)* 2 v det2_8 4.59 4.77 4.95 figure 5.41 v det2_9 4.05 4.23 4.41 v det2_a 4.32 4.50 4.68 internal reset time power-on reset (por) t por 9.7 ms figure 5.38 voltage detection circuit (lvd0) t lvo0 9.7 figure 5.39 voltage detection circuit (lvd1) t lvo1 0.9 figure 5.40 voltage detection circuit (lvd2) t lvo2 0.9 figure 5.41 minimum vcc down time* 3 t voff 200 ? ? s figure 5.39 to figure 5.43 response delay time t det 200 s lvd operation stabilization time (after lvd is enabled) td (e-a) 3 s figure 5.40, figure 5.41 hysteresis width (lvd1 and lvd2) v lvh 80 mv
r01ds0255ej0100 rev.1.00 page 97 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.38 power-on reset timing figure 5.39 voltage detection circuit timing (v det0 ) internal reset signal (active-low) vcc t voff t det t por t det t por t det v por t voff t lvd0 t det v det0 vcc internal reset signal (active-low)
r01ds0255ej0100 rev.1.00 page 98 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.40 voltage detection circuit timing (v det1 ) figure 5.41 voltage detection circuit timing (v det2 ) t voff v det1_# (# = 8, 9, a) vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2_# (# = 8, 9, a) vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0255ej0100 rev.1.00 page 99 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.7 oscillation stop detection timing figure 5.42 oscillation stop detection timing table 5.36 oscillation stop detection circuit characteristics conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.42 t dr main clock or pll clock ostdsr.ostdf loco clock iclk
r01ds0255ej0100 rev.1.00 page 100 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.8 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasi ng can be performed n times for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle i s counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. this result is obtai ned from reliability testing. table 5.37 rom (flash memory for code storage) characteristics (1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +85c t a is common to both conditions 1 and 2. item symbol min. typ. max. unit test conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data hold time t drp 30* 2 ??y e a rt a = +85 c table 5.38 rom (flash memory for code storage) characteristics (2) note: the standard values of the items with no conditions specified in the table are common to conditions 1 and 2. conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +85c t a is common to both conditions 1 and 2. item symbol fclk = 4 mhz 20 mhz fclk 32 mhz unit min. typ. max. min. typ. max. programming time when n pec 100 times 128 bytes t p128 ? 2.8 28 ? 1 10 ms 4 kbytes t p4k ?63140?2350ms 16 kbytes t p16k ? 252 560 ? 90 200 ms programming time when n pec > 100 times 128 bytes t p128 ? 3.4 33.6 ? 1.2 12 ms 4 kbytes t p4k ? 75.6 168 ? 27.6 60 ms 16 kbytes t p16k ? 302.4 672 ? 108 240 ms erasure time when n pec 100 times 4 kbytes t e4k ?50120?2560ms 16 kbytes t e16k ? 200 480 ? 100 240 ms erasure time when n pec > 100 times 4 kbytes t e4k ?60144?3072ms 16 kbytes t e16k ? 240 576 ? 120 288 ms suspend delay time during programming t spd ? ? 400 ? ? 120 s first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 300 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.7??1.7ms suspend delay time during erasing (in erasure priority mode) t seed ??1.7??1.7ms fcu reset time t fcur 35 ? ? 35 ? ? s
r01ds0255ej0100 rev.1.00 page 101 of 106 feb 25, 2015 RX634 group 5. electrical characteristics 5.9 e2 dataflash (flash memory fo r code storage) characteristics note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each bl ock. for instance, when 8-byte programming is performed 16 times for different addresses in 128-byte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. this result is obtai ned from reliability testing. table 5.39 e2 dataflash characteristics (1) conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5 v, vrefh = 4.0 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +85c t a is common to both conditions 1 and 2. item symbol min. typ. max. unit test conditions reprogramming/erasure cycle* 1 n dpec 100000 ? ? times data hold time t ddrp 30* 2 ? ? year t a = +85 c table 5.40 e2 dataflash characteristics (2) note: the standard values of the items with no conditions specified in the table are common to conditions 1 and 2. conditions 1: vcc = avcc0 = vrefh0 = 2.7 to 3.6v, vref h = 2.7v to avcc0, vss = avss0 = vrefl = vrefl0 = 0v conditions 2: vcc = avcc0 = vrefh0 = 4.0 to 5.5v, vref h = 4.0v to avcc0, vss = avss0 = vrefl = vrefl0 = 0v temperature range for the programming/erasure operation: t a = ?40 to +85c t a is common to both conditions 1 and 2. item symbol fclk = 4 mhz 20 mhz fclk 32 mhz unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t dp2 ? 0.7 6 ? 0.25 2 ms programming time when n pec > 100 times 2 bytes t dp2 ? 0.7 6 ? 0.25 2 ms erasure time when n pec 100 times 32 bytes t de32 ?440?220ms erasure time when n pec > 100 times 32 bytes t de32 ?740?420ms blank check time 2 bytes t dbc2 ??100??30 s suspend delay time during programming t dspd ? ? 250 ? ? 120 s first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 250 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t dsesd2 ? ? 500 ? ? 300 s suspend delay time during erasing (in erasure priority mode) t dseed ? ? 500 ? ? 300 s
r01ds0255ej0100 rev.1.00 page 102 of 106 feb 25, 2015 RX634 group 5. electrical characteristics figure 5.43 flash memory pr ogram/erase suspend timing fcu command fstatr0.frdy programming pulse ? suspension during programming fcu command fstatr0.frdy erasure pulse ? suspension during erasure in suspend priority mode fcu command fstatr0.frdy erasure pulse ? suspension during erasure in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0255ej0100 rev.1.00 page 103 of 106 feb 25, 2015 RX634 group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 144-pin lqfp (plqp0144ka-a) terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.270.220.17 maxnommin dimension in millimeters symbol reference 20.120.019.9 d 20.120.019.9 e 1.4 a 2 22.222.021.8 22.222.021.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lfqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 *1 *2 *3 x index mark h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. e y s s
r01ds0255ej0100 rev.1.00 page 104 of 106 feb 25, 2015 RX634 group revision history classifications - items with technical update document number: changes according to the corresponding i ssued technical update - items without technical update documen t number: minor changes that do not re quire technical update to be issued revision history RX634 group datasheet rev. date description classification page summary 1.00 feb 25, 2014 ? first edition, issued all trademarks and registered trademarks are the property of thei r respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rig hts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have sp ecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibi lity of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactur e, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or other wise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this docu ment or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-own ed subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 9251 yonge street, suite 8309 richmond hill, ontario canada l4c 9t3 tel: +1-905-237-2004 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal ii stage, indiranagar, bangalore, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2015 renesas electronics corporation. all rights reserved. colophon 5.0

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